Change in coreboot[master]: soc/broadwell: add missing USB port defs

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19968 )

Change subject: soc/broadwell: add missing USB port defs
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soc/broadwell: add missing USB port defs

Add device/address stubs for XHCI USB ports 7/8, 10-15.
Stub data will be supplemented by board-specific info
added in subsequent commits.

Change-Id: Ice86bd226a70bd5996430e7a68a026cc825ba187
Signed-off-by: Matt DeVillier 
Reviewed-on: https://review.coreboot.org/19968
Reviewed-by: Martin Roth 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/broadwell/acpi/xhci.asl
1 file changed, 8 insertions(+), 1 deletion(-)

Approvals:
  Martin Roth: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl
index a70ded9..53b3956 100644
--- a/src/soc/intel/broadwell/acpi/xhci.asl
+++ b/src/soc/intel/broadwell/acpi/xhci.asl
@@ -355,12 +355,19 @@
    {
    	Name (_ADR, 0x00000000)

-		// How many are there?
    	Device (PRT1) { Name (_ADR, 1) } // USB Port 0
    	Device (PRT2) { Name (_ADR, 2) } // USB Port 1
    	Device (PRT3) { Name (_ADR, 3) } // USB Port 2
    	Device (PRT4) { Name (_ADR, 4) } // USB Port 3
    	Device (PRT5) { Name (_ADR, 5) } // USB Port 4
    	Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+		Device (PRT7) { Name (_ADR, 7) } // USB Port 6
+		Device (PRT8) { Name (_ADR, 8) } // USB Port 7
+		Device (SSP1) { Name (_ADR, 10) } // USB Port 10
+		Device (SSP2) { Name (_ADR, 11) } // USB Port 11
+		Device (SSP3) { Name (_ADR, 12) } // USB Port 12
+		Device (SSP4) { Name (_ADR, 13) } // USB Port 13
+		Device (SSP5) { Name (_ADR, 14) } // USB Port 14
+		Device (SSP6) { Name (_ADR, 15) } // USB Port 15
    }
 }