Michael has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44639 )
Change subject: superio/ite: delay PWRGD3 during resume ......................................................................
superio/ite: delay PWRGD3 during resume
According to the IT8728F datasheet it is possible to add an extra delay between 3VSBSW# being set and PWRGD3 being set during resume from Suspend-to-RAM. This is enabled in the special function selection register, the default being 0.
This is also useful for the IT8720F although this chip does not have the PWRGD3 output. On the corresponding pin it has PWROK2, which the setting then seems to apply to.
The datasheet for the IT8720F marks the corresponding bit as reserved, but the vendor BIOS of an Acer Aspire M3800 sets it anyway. Without setting the bit, coreboot fails to resume from S3. Oscilloscope measurements have shown that setting the bit increases the delay between 3VSBSW# being set and PWROK2 being set from around 1 us to 140 ms. The actual use of PWROK2 on the board design is unclear - the only destination it seems to reach is a pin header near the SuperIO marked as "GPIO1".
Signed-off-by: Michael Büchler michael.buechler@posteo.net Change-Id: I51cbf2470dc2b840a647a20090acb5a0cf4f4025 --- M src/superio/ite/common/early_serial.c M src/superio/ite/common/ite.h 2 files changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44639/1
diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index d19548e..48e414b 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -95,6 +95,33 @@ }
/* + * + * LDN 7, reg 0x2a, bit 0 - delay PWRGD3 rising edge after 3VSBSW# rising edge + * This can be needed for S3 resume. + * Documented in IT8728F V0.4.2 but also applies to IT8720F where it is marked + * as reserved. + * + * Delay PWRGD3 assertion after setting 3VSBSW#. + * 0: There will be no extra delay before PWRGD3 is set. + * 1: The delay after 3VSBSW# rising edge before PWRGD3 is set is increased. + * + * in romstage.c + * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO) + * and pass: GPIO_DEV + */ + +void ite_delay_pwrgd3(pnp_devfn_t dev) +{ + u8 tmp; + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC); + tmp |= 0x01; + pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp); + pnp_exit_conf_state(dev); +} + +/* * in romstage.c * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO) * and pass: GPIO_DEV diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index a0c20ff..3e9b5028 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -15,6 +15,7 @@ /* Some boards need to init wdt+gpio's very early */ void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value); void ite_enable_3vsbsw(pnp_devfn_t dev); +void ite_delay_pwrgd3(pnp_devfn_t dev); void ite_kill_watchdog(pnp_devfn_t dev);
void pnp_enter_conf_state(pnp_devfn_t dev);
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44639 )
Change subject: superio/ite: delay PWRGD3 during resume ......................................................................
Patch Set 1: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44639 )
Change subject: superio/ite: delay PWRGD3 during resume ......................................................................
superio/ite: delay PWRGD3 during resume
According to the IT8728F datasheet it is possible to add an extra delay between 3VSBSW# being set and PWRGD3 being set during resume from Suspend-to-RAM. This is enabled in the special function selection register, the default being 0.
This is also useful for the IT8720F although this chip does not have the PWRGD3 output. On the corresponding pin it has PWROK2, which the setting then seems to apply to.
The datasheet for the IT8720F marks the corresponding bit as reserved, but the vendor BIOS of an Acer Aspire M3800 sets it anyway. Without setting the bit, coreboot fails to resume from S3. Oscilloscope measurements have shown that setting the bit increases the delay between 3VSBSW# being set and PWROK2 being set from around 1 us to 140 ms. The actual use of PWROK2 on the board design is unclear - the only destination it seems to reach is a pin header near the SuperIO marked as "GPIO1".
Signed-off-by: Michael Büchler michael.buechler@posteo.net Change-Id: I51cbf2470dc2b840a647a20090acb5a0cf4f4025 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44639 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/superio/ite/common/early_serial.c M src/superio/ite/common/ite.h 2 files changed, 28 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index d19548e..48e414b 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -95,6 +95,33 @@ }
/* + * + * LDN 7, reg 0x2a, bit 0 - delay PWRGD3 rising edge after 3VSBSW# rising edge + * This can be needed for S3 resume. + * Documented in IT8728F V0.4.2 but also applies to IT8720F where it is marked + * as reserved. + * + * Delay PWRGD3 assertion after setting 3VSBSW#. + * 0: There will be no extra delay before PWRGD3 is set. + * 1: The delay after 3VSBSW# rising edge before PWRGD3 is set is increased. + * + * in romstage.c + * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO) + * and pass: GPIO_DEV + */ + +void ite_delay_pwrgd3(pnp_devfn_t dev) +{ + u8 tmp; + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC); + tmp |= 0x01; + pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp); + pnp_exit_conf_state(dev); +} + +/* * in romstage.c * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO) * and pass: GPIO_DEV diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index a0c20ff..3e9b5028 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -15,6 +15,7 @@ /* Some boards need to init wdt+gpio's very early */ void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value); void ite_enable_3vsbsw(pnp_devfn_t dev); +void ite_delay_pwrgd3(pnp_devfn_t dev); void ite_kill_watchdog(pnp_devfn_t dev);
void pnp_enter_conf_state(pnp_devfn_t dev);
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44639 )
Change subject: superio/ite: delay PWRGD3 during resume ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 6/1/7 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/16139 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/16138 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/16137 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/16136 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/16135 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/16141 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/16140
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Felix Held (Code Review)
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Michael (Code Review)