Change in coreboot[master]: soc/amd/cezanne/Kconfig: select IDT_IN_EVERY_STAGE

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49726 )

Change subject: soc/amd/cezanne/Kconfig: select IDT_IN_EVERY_STAGE
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soc/amd/cezanne/Kconfig: select IDT_IN_EVERY_STAGE

This adds interrupt handlers that end up calling x86_exception().

Change-Id: I3dce539b6f1ef300cf16f20224744a75100f60b8
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49726
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 50b8777..1a38c77 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -14,6 +14,7 @@
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
    select HAVE_CF9_RESET
+	select IDT_IN_EVERY_STAGE
    select IOAPIC
    select RESET_VECTOR_IN_RAM
    select SOC_AMD_COMMON