Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, Felix Held.
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )

Change subject: soc/intel/elkhartlake: Introduce Intel PSE
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Patch Set 51:

(1 comment)

File src/soc/intel/elkhartlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/55367/comment/dde69c31_0df4093d 
PS49, Line 127: 	m_cfg->PchPseEnable = CONFIG(PSE_ENABLE);
> I don't know what OK means on your scale. You outrank me anyway, so […]

Hi Nico, thanks for your feedback on this. Although it always brought be little worries when seeing your review but I do agree your concerns were pretty valid most of the times. And with yours and few other folks reviews (Paul, Filix, Arthur, Angels, Michael) have already made this patch much better than its original patch, once again much appreciated all your hard work and i did learn a few things here 😜
Werner has also put a lot of commitment and hardwork in the back to address this PSE blob mess. It was not easy but the right things have to be done, and I also respect him for that.

Back to this issue, Werner and I were concerned about this, and we are trying to see if a new cbfs API like 'cbfs_check' could be create for this.