Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik.
Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83938?usp=email )
Change subject: mb/google/fatcat: Update dsdt.asl to include soc/intel/ptl/acpi ......................................................................
mb/google/fatcat: Update dsdt.asl to include soc/intel/ptl/acpi
Details: - This patch adds soc acpi file entry in mainboard dsdt.asl - PTL replaces DMI3 with SAF, to ensure common/block/acpi/acpi/northbridge.asl binding with PTL change, #if DMI_BASE_SIZE gaurd check is added in northbridge.asl
BUG=b:348678529 TEST=Able to build the google/fatcat and boot to bootblock stage using Intel® Simics® Pre Silicon Simulation platform for PTL.
Change-Id: I284a1eba19c03008f3e57f1427a72affb2129a8b Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com --- M src/mainboard/google/fatcat/dsdt.asl M src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/pantherlake/include/soc/iomap.h 4 files changed, 38 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/83938/1
diff --git a/src/mainboard/google/fatcat/dsdt.asl b/src/mainboard/google/fatcat/dsdt.asl index 2c714d7..991936b 100644 --- a/src/mainboard/google/fatcat/dsdt.asl +++ b/src/mainboard/google/fatcat/dsdt.asl @@ -2,6 +2,7 @@
#include <acpi/acpi.h> #include <variant/ec.h> +#include <variant/gpio.h>
DefinitionBlock( "dsdt.aml", @@ -9,8 +10,33 @@ ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, - 0x20110725 + 0x20110725 /* OEM revision */ ) { - /* TODO: Add ACPI code as per board design */ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/pantherlake/acpi/southbridge.asl> + /* TODO: Add tcss.asl */ + } + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h index e468198..4696bf3 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h +++ b/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h @@ -6,5 +6,10 @@ #include <baseboard/gpio.h>
/* TODO: Add GPIO as per fatcat board */ +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK
#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 51b0e23..dc48857 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -291,12 +291,12 @@ * B0:D0:F0:Reg.48h */ Memory32Fixed (ReadWrite, 0, MCH_BASE_SIZE, MCHB) - +#if DMI_BASE_SIZE /* DMI BAR _BAS will be updated in _CRS below according to * B0:D0:F0:Reg.68h */ Memory32Fixed (ReadWrite, 0, DMI_BASE_SIZE, DMIB) - +#endif /* EP BAR _BAS will be updated in _CRS below according to * B0:D0:F0:Reg.40h */ diff --git a/src/soc/intel/pantherlake/include/soc/iomap.h b/src/soc/intel/pantherlake/include/soc/iomap.h index dbabfd6..7c02765 100644 --- a/src/soc/intel/pantherlake/include/soc/iomap.h +++ b/src/soc/intel/pantherlake/include/soc/iomap.h @@ -20,6 +20,9 @@ #define SAF_BASE_ADDRESS 0x3ffe000000 #define SAF_BASE_SIZE 0x2000000
+/* Add DMI entry to cater common/block/acpi/acpi/northbridge.asl */ +#define DMI_BASE_SIZE 0 + #define EP_BASE_ADDRESS 0xfeda1000 #define EP_BASE_SIZE 0x1000