[S] Change in coreboot[main]: nb/via/cx700: Implement FSB tuning

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82769?usp=email )

Change subject: nb/via/cx700: Implement FSB tuning
......................................................................

nb/via/cx700: Implement FSB tuning

This northbridge provides a lot of knobs for fine-grained tuning of the
FSB drivers. The programming manual calls this "Host AGTL+ I/O Driving
Control". We program the known good values for use with a VIA C7 CPU,
and warn about use with different CPUs.

The numbers were pulled out of raminit of the original CX700 port.
Originally, there was a write to 0x83 as well, to set bit 1 which
triggers a soft reset of the CPU.  It was amidst a table, so it
seems unclear if it was put there intentionally.

Change-Id: I24ba6cfaab2ca3069952a6c399a065caea7b49f2
Signed-off-by: Nico Huber 
---
M src/northbridge/via/cx700/romstage.c
1 file changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/82769/1

diff --git a/src/northbridge/via/cx700/romstage.c b/src/northbridge/via/cx700/romstage.c
index f4c5584..f6999a3 100644
--- a/src/northbridge/via/cx700/romstage.c
+++ b/src/northbridge/via/cx700/romstage.c
@@ -1,10 +1,53 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <stddef.h>
+#include <stdint.h>
+#include <commonlib/bsd/helpers.h>
+#include <device/pci_ops.h>
+#include <static_devices.h>
 #include <romstage_common.h>
 #include <halt.h>

+static void tune_fsb(void)
+{
+	if (!CONFIG(CPU_VIA_C7)) {
+		printk(BIOS_WARNING,
+		       "FSB settings are known for VIA C7 CPUs, P4 compat. is unknown.\n");
+	}
+	static const struct {
+		uint8_t reg;
+		uint8_t val;
+	} fsb_settings[] = {
+		{ 0x70, 0x33 },
+		{ 0x71, 0x11 },
+		{ 0x72, 0x33 },
+		{ 0x73, 0x11 },
+		{ 0x74, 0x20 },
+		{ 0x75, 0x2e },
+		{ 0x76, 0x64 },
+		{ 0x77, 0x00 },
+		{ 0x78, 0x44 },
+		{ 0x79, 0xaa },
+		{ 0x7a, 0x33 },
+		{ 0x7b, 0xaa },
+		{ 0x7c, 0x00 },
+		{ 0x7e, 0x33 },
+		{ 0x7f, 0x33 },
+		{ 0x80, 0x44 },
+		{ 0x81, 0x44 },
+		{ 0x82, 0x44 },
+	};
+	for (size_t i = 0; i < ARRAY_SIZE(fsb_settings); ++i)
+		pci_write_config8(_sdev_host_if, fsb_settings[i].reg, fsb_settings[i].val);
+}
+
 void __noreturn romstage_main(void)
 {
+	/* Allows access to all northbridge PCI devfn's */
+	pci_write_config8(_sdev_host_ctrl, 0x4f, 0x01);
+
+	tune_fsb();
+
    /* Needed for __noreturn */
    halt();
 }