Change in coreboot[master]: amd/stoneyridge: Make cbmem_top SMM aware

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21491

Change subject: amd/stoneyridge: Make cbmem_top SMM aware
......................................................................

amd/stoneyridge: Make cbmem_top SMM aware

Make the default for SMM_TSEG_SIZE depend on SMM_TSEG in addition to
HAVE_SMI_HANDLER.

Change the value returned by cbmem_top() to carve out a range to be
used by TSEG.  Align the value to 128KB to match the granularity of
the TSegBase field.

Change-Id: I54ffc10108862b7d022fbbd92bf97525b349df27
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/ramtop.c
2 files changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/21491/1

diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 08613fe..f8768e7 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -289,7 +289,7 @@

config SMM_TSEG_SIZE
    hex
-	default 0x800000 if HAVE_SMI_HANDLER
+	default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER
    default 0x0

config ACPI_CPU_STRING
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index c81e73b..bbe11d2 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -41,5 +41,6 @@
    if (!tom.lo)
    	return 0;
    else
-		return (void *)restore_top_of_low_cacheable();
+		return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
+				- CONFIG_SMM_TSEG_SIZE, 128*KiB);
 }