Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56814 )
Change subject: soc/amd/common/block/spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST ......................................................................
soc/amd/common/block/spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST
Add a new Kconfig option to enable or disable the 4 DWORD burst support of the SPI controller and use this setting to determine if the corresponding feature bit in SPI100_HOST_PREF_CONFIG will be set or cleared. Since fch_spi_disable_4dw_burst can now enable or disable the feature, rename it to fch_spi_configure_4dw_burst. On Stoneyridge the SPI_RD4DW_EN_HOST bit needs to be cleared (see the Rd4dw_en_host bit definition in the SPIx2C SPI100 Host Prefetch Config register in the public BKDG #55072 Rev 3.09), so add a SoC dependency to the Kconfig option.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Id754fa8d5f9554ed25cf9f3341bfdd1968693788 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56814 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Jason Glenesk jason.glenesk@gmail.com Reviewed-by: Paul Menzel paulepanter@mailbox.org --- M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/common/block/spi/fch_spi.c 2 files changed, 14 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig index fa24f83..eb5412f 100644 --- a/src/soc/amd/common/block/spi/Kconfig +++ b/src/soc/amd/common/block/spi/Kconfig @@ -8,6 +8,12 @@ config SOC_AMD_COMMON_BLOCK_SPI_DEBUG bool
+config SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST + bool + depends on !SOC_AMD_STONEYRIDGE + help + Select this option to keep the 4 DWORD burst support enabled. + config EFS_SPI_READ_MODE int range 0 7 diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index 0351847..7ef9839 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -15,11 +15,16 @@ spi_write16(SPI100_ENABLE, SPI_USE_SPI100); }
-static void fch_spi_disable_4dw_burst(void) +static void fch_spi_configure_4dw_burst(void) { uint16_t val = spi_read16(SPI100_HOST_PREF_CONFIG);
- spi_write16(SPI100_HOST_PREF_CONFIG, val & ~SPI_RD4DW_EN_HOST); + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST)) + val |= SPI_RD4DW_EN_HOST; + else + val &= ~SPI_RD4DW_EN_HOST; + + spi_write16(SPI100_HOST_PREF_CONFIG, val); }
static void fch_spi_set_read_mode(u32 mode) @@ -61,6 +66,6 @@ { lpc_enable_spi_rom(SPI_ROM_ENABLE); lpc_enable_spi_prefetch(); - fch_spi_disable_4dw_burst(); + fch_spi_configure_4dw_burst(); fch_spi_config_modes(); }