Shon Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60251 )
Change subject: mb/google/brya/var/vell: update overridetree for touchpad ......................................................................
mb/google/brya/var/vell: update overridetree for touchpad
update override devicetree for touchpad based on schematics
BUG=b:209489126 TEST=emerge-brya coreboot
Signed-off-by: Shon Wang shon.wang@quanta.corp-partner.google.com Change-Id: Icd2f5de38df0eb89fb92ea2abe25851c0d6ec53f --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 51 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/60251/1
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 4006af8..6c624b2 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -46,9 +46,17 @@ #| | for TPM communication | #| I2C5 | Trackpad | #+-------------------+---------------------------+ - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "common_soc_config" = "{ + .i2c[0] = { + .rise_time_ns = 550, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + .speed = I2C_SPEED_FAST, + }, + }" + + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)" # USB2_C3 + # I2C Port Config register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -64,7 +72,7 @@ register "device_count" = "1" register "device[0].name" = ""LCD"" # Use Chrome OS privacy screen _HID - register "device[0].hid" = ""GOOG0010"" + #register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" register "device[0].privacy.enabled" = "1" @@ -125,7 +133,7 @@ end end device ref pcie4_0 on - # Enable CPU PCIE RP 1 using CLK 1 + # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 1, .clk_src = 1, @@ -226,7 +234,8 @@ register "generic.wake" = "GPE0_DW2_14" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 15 on end + device i2c 15 on + end end end device ref gspi1 on @@ -244,6 +253,8 @@ chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + use conn3 as mux_conn[3] device pnp 0c09.0 on end end end @@ -256,9 +267,19 @@ device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "2" + register "usb3_port_number" = "2" + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "3" register "usb3_port_number" = "3" - device generic 1 alias conn1 on end + device generic 2 alias conn2 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "5" + register "usb3_port_number" = "4" + device generic 3 alias conn3 on end end end end @@ -273,11 +294,23 @@ device ref tcss_usb3_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "desc" = ""USB3 Type-C Port C1 (MlB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(3, 1)" device ref tcss_usb3_port3 on end end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C3 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref tcss_usb3_port4 on end + end end end end @@ -291,11 +324,11 @@ device ref usb2_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port (MLB)"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 2)" + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb2_port2 on end - end + end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" @@ -308,36 +341,17 @@ device ref usb2_port4 on end end chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C3 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi register "desc" = ""USB2 Camera"" register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port6 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port (DB)"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" - device ref usb2_port9 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" - device ref usb2_port10 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port (DB)"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" - device ref usb3_port1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port (MLB)"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 2)" - device ref usb3_port3 on end - end - chip drivers/usb/acpi register "desc" = ""USB3 WWAN"" register "type" = "UPC_TYPE_INTERNAL" device ref usb3_port4 on end
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Shon Wang (Code Review)