Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42687 )
Change subject: soc/amd/common: Refactor GPIO SCI/SMI interrupts ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/42687/5/src/soc/amd/common/block/gp... File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42687/5/src/soc/amd/common/block/gp... PS5, Line 52: sci_trigger_regs Since you are deleting the SCI_TRIGGER_X macros, you add a comment saying 0 -> Low, 1 -> High for the polarity, and 0 -> Edge, 1 -> Level for the level field.
https://review.coreboot.org/c/coreboot/+/42687/5/src/soc/amd/common/block/gp... PS5, Line 55: level Can you name this trigger? Level makes me think Level high or Level low. Trigger makes me think edge or level.
https://review.coreboot.org/c/coreboot/+/42687/5/src/soc/amd/common/block/gp... PS5, Line 94: SMI_SCI_LEVEL I hate the name of these registers.
https://review.coreboot.org/c/coreboot/+/42687/5/src/soc/amd/common/block/gp... PS5, Line 190: { 0 }. { } is not a valid C standard construct, but a GCC extension.