Change in coreboot[master]: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register
Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/broadwell/adsp.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41009/1
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 64b7d5e..1f5f814 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -118,7 +118,7 @@ printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n");
/* Configure for PCI mode */ - pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); + pci_write_config8(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ);
/* Clear ACPI Interrupt Enable Bit */ pch_iobp_update(ADSP_IOBP_PCICFGCTL,
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
Patch Set 1: Code-Review+1
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
Patch Set 1:
Thx
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41009/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41009/1//COMMIT_MSG@8 PS1, Line 8: Maybe add:
The PCI_INTERRUPT_LINE register is one byte wide.
Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41009
to look at the new patch set (#2).
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register
The PCI_INTERRUPT_LINE register is one byte wide.
Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/broadwell/adsp.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41009/2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41009/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41009/1//COMMIT_MSG@8 PS1, Line 8:
Maybe add: […]
Thx
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
Patch Set 2: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41009/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41009/2//COMMIT_MSG@9 PS2, Line 9: The PCI_INTERRUPT_LINE register is one byte wide. Please mention possible effects of the wrong write. I assume the other registers that were originally written (accidentally cleared) are all read-only, but we don't know that until somebody tries.
If we don't know and don't want to try, we should at least mention that "Possible side-effects are unknown.".
Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41009
to look at the new patch set (#3).
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register
The PCI_INTERRUPT_LINE register is one byte wide.
Possible side-effects are unknown: Originally written registers (accidentally cleared) are all read-only, but we don't know that until somebody tries.
Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/broadwell/adsp.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41009/3
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41009/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41009/2//COMMIT_MSG@9 PS2, Line 9: The PCI_INTERRUPT_LINE register is one byte wide.
Please mention possible effects of the wrong write. I assume the […]
Done. Vielen Dank
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41009/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41009/3//COMMIT_MSG@12 PS3, Line 12: Originally written registers (accidentally cleared) : are all read-only You copy-pasted this out of context and now it's wrong.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41009/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41009/3//COMMIT_MSG@11 PS3, Line 11: Possible side-effects are unknown: Possible side effects of clearing the three bytes after PCI_INTERRUPT_LINE are unknown.
Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41009
to look at the new patch set (#4).
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register
The PCI_INTERRUPT_LINE register is one byte wide.
Possible side-effects are unknown.
Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/broadwell/adsp.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41009/4
Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41009
to look at the new patch set (#5).
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register
The PCI_INTERRUPT_LINE register is one byte wide. Possible side effects of clearing the three bytes after PCI_INTERRUPT_LINE are unknown.
Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/broadwell/adsp.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41009/5
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41009/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41009/3//COMMIT_MSG@11 PS3, Line 11: Possible side-effects are unknown:
Possible side effects of clearing the three bytes after PCI_INTERRUPT_LINE are unknown.
Done
https://review.coreboot.org/c/coreboot/+/41009/3//COMMIT_MSG@12 PS3, Line 12: Originally written registers (accidentally cleared) : are all read-only
You copy-pasted this out of context and now it's wrong.
Done
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41009/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41009/2//COMMIT_MSG@9 PS2, Line 9: The PCI_INTERRUPT_LINE register is one byte wide.
Done. […]
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register
The PCI_INTERRUPT_LINE register is one byte wide. Possible side effects of clearing the three bytes after PCI_INTERRUPT_LINE are unknown.
Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/41009 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/broadwell/adsp.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 27368c0..897f9c4 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -115,7 +115,7 @@ printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n");
/* Configure for PCI mode */ - pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); + pci_write_config8(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ);
/* Clear ACPI Interrupt Enable Bit */ pch_iobp_update(ADSP_IOBP_PCICFGCTL,
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)