Hello Patrick Georgi, Martin Roth,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31813
to review the following change.
Change subject: Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX) ......................................................................
Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few).
Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/arm/armv7/mmu.c M src/arch/x86/failover.ld M src/arch/x86/memlayout.ld M src/commonlib/storage/sdhci.c M src/cpu/amd/family_10h-family_15h/fidvid.c M src/cpu/amd/quadcore/amd_sibling.c M src/cpu/intel/hyperthreading/intel_sibling.c M src/device/device.c M src/drivers/intel/wifi/wifi.c M src/drivers/pc80/pc/keyboard.c M src/include/device/hypertransport_def.h M src/include/device/i2c_simple.h M src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c M src/mainboard/amd/olivehillplus/BiosCallOuts.c M src/mainboard/amd/torpedo/gpio.c M src/mainboard/bap/ode_e21XX/BiosCallOuts.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu2/BiosCallOuts.c M src/northbridge/amd/amdfam10/northbridge.c M src/northbridge/amd/pi/agesawrapper.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/pei_data.c M src/soc/nvidia/tegra124/bootblock.c M src/soc/nvidia/tegra210/bootblock.c M src/southbridge/amd/cimx/sb800/cfg.c M src/southbridge/amd/cimx/sb900/early.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/nvidia/ck804/ck804.h 33 files changed, 53 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31813/1
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 14f5f7a..ce9d3fd 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -277,7 +277,7 @@ for (; (pte_t *)_ettb_subtables - table > 0; table += SUBTABLE_PTES) table[0] = ATTR_UNUSED;
- if (CONFIG_ARM_LPAE) { + if (CONFIG(ARM_LPAE)) { pte_t *const pgd_buff = (pte_t *)(_ttb + 16*KiB); pte_t *pmd = ttb_buff; int i; @@ -331,7 +331,7 @@ * See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected. */ write_ttbcr( - CONFIG_ARM_LPAE << 31 | /* EAE. 1:Enable LPAE */ + CONFIG(ARM_LPAE) << 31 |/* EAE. 1:Enable LPAE */ 0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */ );
diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index b32aa29..a9a5942 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -28,7 +28,7 @@ * boundary anyway, so no pad byte appears between _rom and _start. */ .bogus ROMLOC_MIN : { - . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); + . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(4); ROMLOC = .; } >rom = 0xff
@@ -50,10 +50,10 @@ * address gets applied. */ ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); + (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 0);
/* Post-check proper SIPI vector. */ - _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff), + _bogus = ASSERT(!CONFIG(SIPI_VECTOR_IN_ROM) || (ap_sipi_vector_in_rom == 0xff), "Address mismatch on AP_SIPI_VECTOR");
/DISCARD/ : { diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 8e073f2..cc72552 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -26,7 +26,7 @@ * conditionalize with macros. */ #if ENV_RAMSTAGE - RAMSTAGE(CONFIG_RAMBASE, (CONFIG_RELOCATABLE_RAMSTAGE ? 8M : + RAMSTAGE(CONFIG_RAMBASE, (CONFIG(RELOCATABLE_RAMSTAGE) ? 8M : CONFIG_RAMTOP - CONFIG_RAMBASE))
#elif ENV_ROMSTAGE diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 8482488..3f270e8 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -32,9 +32,9 @@ #include <timer.h> #include <commonlib/stdlib.h>
-#define DMA_AVAILABLE ((CONFIG_SDHCI_ADMA_IN_BOOTBLOCK && ENV_BOOTBLOCK) \ - || (CONFIG_SDHCI_ADMA_IN_VERSTAGE && ENV_VERSTAGE) \ - || (CONFIG_SDHCI_ADMA_IN_ROMSTAGE && ENV_ROMSTAGE) \ +#define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \ + || (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_VERSTAGE) \ + || (CONFIG(SDHCI_ADMA_IN_ROMSTAGE) && ENV_ROMSTAGE) \ || ENV_POSTCAR || ENV_RAMSTAGE)
__weak void *dma_malloc(size_t length_in_bytes) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index db58f5d..579cae5 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -1084,7 +1084,7 @@ init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, -1, init_fidvid_bsp_stage1, &fv); + for_each_ap(bsp_apicid, CONFIG(SET_FIDVID_CORE0_ONLY), -1, init_fidvid_bsp_stage1, &fv); #endif
print_debug_fv("common_fid = ", fv.common_fid); diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index 000cb88..f9aba51 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -74,7 +74,7 @@ u32 siblings; u32 nb_cfg_54;
- u32 disable_siblings = !CONFIG_LOGICAL_CPUS; + u32 disable_siblings = !CONFIG(LOGICAL_CPUS);
get_option(&disable_siblings, "multi_core");
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index f2f28f6..e634f85 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -24,7 +24,7 @@ #endif
static int first_time = 1; -static int disable_siblings = !CONFIG_LOGICAL_CPUS; +static int disable_siblings = !CONFIG(LOGICAL_CPUS);
/* Return true if running thread does not have the smallest lapic ID * within a CPU core. diff --git a/src/device/device.c b/src/device/device.c index ae0dbdb..1b4255b 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -790,12 +790,12 @@ if (!vga) vga = vga_onboard;
- if (CONFIG_ONBOARD_VGA_IS_PRIMARY && vga_onboard) + if (CONFIG(ONBOARD_VGA_IS_PRIMARY) && vga_onboard) vga = vga_onboard;
/* If we prefer plugin VGA over chipset VGA, the chipset might want to know. */ - if (!CONFIG_ONBOARD_VGA_IS_PRIMARY && (vga != vga_onboard) && + if (!CONFIG(ONBOARD_VGA_IS_PRIMARY) && (vga != vga_onboard) && vga_onboard && vga_onboard->ops && vga_onboard->ops->disable) { printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n"); vga_onboard->ops->disable(vga_onboard); diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index d78b007..c0f665f 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -101,7 +101,7 @@ package_size = 1 + 1 + BYTES_PER_SAR_LIMIT; acpigen_write_package(package_size); acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI); - acpigen_write_dword(CONFIG_SAR_ENABLE); + acpigen_write_dword(CONFIG(SAR_ENABLE)); for (i = 0; i < BYTES_PER_SAR_LIMIT; i++) acpigen_write_byte(sar_limits.sar_limit[0][i]); acpigen_pop_len(); @@ -130,7 +130,7 @@ package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT; acpigen_write_package(package_size); acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI); - acpigen_write_dword(CONFIG_DSAR_ENABLE); + acpigen_write_dword(CONFIG(DSAR_ENABLE)); acpigen_write_dword(CONFIG_DSAR_SET_NUM); for (i = 1; i < NUM_SAR_LIMITS; i++) for (j = 0; j < BYTES_PER_SAR_LIMIT; j++) diff --git a/src/drivers/pc80/pc/keyboard.c b/src/drivers/pc80/pc/keyboard.c index 3849e73..bfd05c1 100644 --- a/src/drivers/pc80/pc/keyboard.c +++ b/src/drivers/pc80/pc/keyboard.c @@ -249,7 +249,7 @@ enum cb_err err; uint8_t aux_dev_detected;
- if (!CONFIG_DRIVERS_PS2_KEYBOARD) + if (!CONFIG(DRIVERS_PS2_KEYBOARD)) return 0;
if (acpi_is_wakeup_s3()) diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h index 4b340e8..ef9de2c 100644 --- a/src/include/device/hypertransport_def.h +++ b/src/include/device/hypertransport_def.h @@ -23,7 +23,7 @@ { bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); - return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + return need_offset && (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) || is_sb_ht_chain); }
diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h index dcde601..e3cc892 100644 --- a/src/include/device/i2c_simple.h +++ b/src/include/device/i2c_simple.h @@ -54,7 +54,7 @@ static inline int i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count) { - if (CONFIG_SOFTWARE_I2C) + if (CONFIG(SOFTWARE_I2C)) if (bus < SOFTWARE_I2C_MAX_BUS && software_i2c[bus]) return software_i2c_transfer(bus, segments, count);
diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c index 83db64c..1208953 100644 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c @@ -269,7 +269,7 @@ if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c index 2f22f6c..ad5656e 100644 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c @@ -253,7 +253,7 @@ FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index 4a8861c..51e3571 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -340,7 +340,7 @@ // // Enable/Disable OnBoard LAN // - if (!CONFIG_ONBOARD_LAN) + if (!CONFIG(ONBOARD_LAN)) { // 1 - DISABLED RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); @@ -358,7 +358,7 @@ // // Enable/Disable 1394 // - if (!CONFIG_ONBOARD_1394) + if (!CONFIG(ONBOARD_1394)) { // 1 - DISABLED // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off @@ -387,7 +387,7 @@ // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { // disable Onboard NEC USB3.0 controller - if (!CONFIG_ONBOARD_USB30) { + if (!CONFIG(ONBOARD_USB30)) { RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE @@ -401,7 +401,7 @@ // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE // GPIO07: BT_ON, 0 - OFF, 1 - ON // - if (!CONFIG_ONBOARD_BLUETOOTH) { + if (!CONFIG(ONBOARD_BLUETOOTH)) { //- if (SystemConfiguration.amdBlueTooth == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); //- } @@ -412,7 +412,7 @@ // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF // - if (!CONFIG_ONBOARD_WEBCAM) { + if (!CONFIG(ONBOARD_WEBCAM)) { //- if (SystemConfiguration.amdWebCam == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); //- } @@ -423,7 +423,7 @@ // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE // - if (!CONFIG_ONBOARD_TRAVIS) { + if (!CONFIG(ONBOARD_TRAVIS)) { //- if (SystemConfiguration.amdTravisCtrl == 0) { RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); //- } @@ -432,7 +432,7 @@ // // Disable Light Sensor if needed // - if (CONFIG_ONBOARD_LIGHTSENSOR) { + if (CONFIG(ONBOARD_LIGHTSENSOR)) { //- if (SystemConfiguration.amdLightSensor == 1) { RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); //- } diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 18e5b7c..6e07525 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -255,7 +255,7 @@ FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 10460bd..e71a778 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -139,16 +139,16 @@ uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0); if (uart) - uart->enabled = CONFIG_APU1_PINMUX_UART_C; + uart->enabled = CONFIG(APU1_PINMUX_UART_C); if (gpio) - gpio->enabled = CONFIG_APU1_PINMUX_GPIO0; + gpio->enabled = CONFIG(APU1_PINMUX_GPIO0);
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1); if (uart) - uart->enabled = CONFIG_APU1_PINMUX_UART_D; + uart->enabled = CONFIG(APU1_PINMUX_UART_D); if (gpio) - gpio->enabled = CONFIG_APU1_PINMUX_GPIO1; + gpio->enabled = CONFIG(APU1_PINMUX_GPIO1); }
static void pnp_raw_resource(struct device *dev, u8 reg, u8 val) @@ -165,11 +165,11 @@ struct device *uart;
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); - if (uart && uart->enabled && CONFIG_UART_C_RS485) + if (uart && uart->enabled && CONFIG(UART_C_RS485)) pnp_raw_resource(uart, 0xf2, 0x12);
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); - if (uart && uart->enabled && CONFIG_UART_D_RS485) + if (uart && uart->enabled && CONFIG(UART_D_RS485)) pnp_raw_resource(uart, 0xf2, 0x12); }
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 3faa462..7d7fc0a 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -69,7 +69,7 @@ FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 16b7bec..1d071c1 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -177,7 +177,7 @@ pci_write_config32(link->dev, link->cap + 0x14, busses);
if (mode == HT_ROUTE_FINAL) { - if (CONFIG_HT_CHAIN_DISTRIBUTE) + if (CONFIG(HT_CHAIN_DISTRIBUTE)) parent->subordinate = ALIGN_UP(link->subordinate, 8) - 1; else parent->subordinate = link->subordinate; @@ -1450,7 +1450,7 @@ siblings = 3; //quad core }
- disable_siblings = !CONFIG_LOGICAL_CPUS; + disable_siblings = !CONFIG(LOGICAL_CPUS); #if CONFIG(LOGICAL_CPUS) get_option(&disable_siblings, "multi_core"); #endif diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 28f2876..1cc7b7c 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -127,7 +127,7 @@
// Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow // the compiler to flag the error if CONFIG_GFXUMA is not set. - PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; + PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; PostParams->MemConfig.BottomIo = (UINT16) (CONFIG_BOTTOMIO_POSITION >> 24); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 633b09d..c72417e 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -677,10 +677,10 @@ if (err == 0) gfx_set_init_done(1); /* Linux relies on VBT for panel info. */ - if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CALISTOGA"); } - if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { generate_fake_intel_oprom(&conf->gfx, dev, "$VBT LAKEPORT-G"); } } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a93cf1e..8c2fe7c 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -286,7 +286,7 @@ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
/* clear self refresh status if check is disabled or not a resume */ - if (!CONFIG_CHECK_SLFRCS_ON_RESUME + if (!CONFIG(CHECK_SLFRCS_ON_RESUME) || sysinfo->boot_path != BOOT_PATH_RESUME) { MCHBAR8(SLFRCS) |= 3; } else { diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index c979897..0166986 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -69,7 +69,7 @@ mainboard_config_superio();
/* USB is initialized in MRC if MRC is used. */ - if (CONFIG_USE_NATIVE_RAMINIT) { + if (CONFIG(USE_NATIVE_RAMINIT)) { early_usb_init(mainboard_usb_ports); }
diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index fc69b46..bb022c7 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -181,7 +181,7 @@
AMD_POST_PARAMS *PostParams = create_struct(&AmdParamStruct);
- PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; + PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; PostParams->MemConfig.BottomIo = (uint16_t) (CONFIG_BOTTOMIO_POSITION >> 24); diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index 53af617..75edb9a 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -47,7 +47,7 @@
static void ehci_enable(struct device *dev) { - if (CONFIG_USBDEBUG) + if (CONFIG(USBDEBUG)) dev->enabled = 1; else pch_disable_devfn(dev); diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index dfaf025..d8059ec 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -30,7 +30,7 @@ { pei_data->pei_version = PEI_VERSION; pei_data->board_type = BOARD_TYPE_ULT; - pei_data->usbdebug = CONFIG_USBDEBUG; + pei_data->usbdebug = CONFIG(USBDEBUG); pei_data->pciexbar = MCFG_BASE_ADDRESS; pei_data->smbusbar = SMBUS_BASE_ADDRESS; pei_data->ehcibar = EARLY_EHCI_BAR; diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 182fadb..c750304 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -64,7 +64,7 @@ pinmux_set_config(PINMUX_UART2_RTS_N_INDEX, PINMUX_UART2_RTS_N_FUNC_UB3);
- if (CONFIG_BOOTBLOCK_CONSOLE) { + if (CONFIG(BOOTBLOCK_CONSOLE)) { console_init(); exception_init(); } diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index 97ea1c9..96fb9b2 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -177,7 +177,7 @@
bootblock_mainboard_early_init();
- if (CONFIG_BOOTBLOCK_CONSOLE) { + if (CONFIG(BOOTBLOCK_CONSOLE)) { console_init(); exception_init(); printk(BIOS_INFO, "T210: Bootblock here\n"); diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 4487df3..b52918d 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -101,7 +101,7 @@ #endif /* LPC */ /* SuperIO hardware monitor register access */ - sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM; + sb_config->SioHwmPortEnable = CONFIG(SB_SUPERIO_HWM);
/* * GPP. default configure only enable port0 with 4 lanes, diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 6fe133b..3b88ff5 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -41,7 +41,7 @@ outb(0xEA, 0xCD6); data = inb(0xCD7); data &= !BIT0; - if (!CONFIG_PCIB_ENABLE) { + if (!CONFIG(PCIB_ENABLE)) { data |= BIT0; } outb(data, 0xCD7); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index f22be9e..f2a9c14 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -418,7 +418,7 @@
static void pch_set_acpi_mode(void) { - if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) { + if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index d440f65..ac45e8f 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -433,7 +433,7 @@
static void pch_set_acpi_mode(void) { - if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) { + if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h index fc99d9a..5505691 100644 --- a/src/southbridge/nvidia/ck804/ck804.h +++ b/src/southbridge/nvidia/ck804/ck804.h @@ -24,7 +24,7 @@ #endif
#define CK804B_BUSN 0x80 -#define CK804B_DEVN_BASE (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY ? CK804_DEVN_BASE : 1) +#define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1)
#ifdef __PRE_RAM__ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31813 )
Change subject: Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX) ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/#/c/31813/1/src/northbridge/intel/i945/gma.c File src/northbridge/intel/i945/gma.c:
https://review.coreboot.org/#/c/31813/1/src/northbridge/intel/i945/gma.c@680 PS1, Line 680: if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/31813/1/src/northbridge/intel/i945/gma.c@683 PS1, Line 683: if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/31813/1/src/northbridge/intel/sandybridge/ro... File src/northbridge/intel/sandybridge/romstage.c:
https://review.coreboot.org/#/c/31813/1/src/northbridge/intel/sandybridge/ro... PS1, Line 72: if (CONFIG(USE_NATIVE_RAMINIT)) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/31813/1/src/southbridge/amd/cimx/sb900/early... File src/southbridge/amd/cimx/sb900/early.c:
https://review.coreboot.org/#/c/31813/1/src/southbridge/amd/cimx/sb900/early... PS1, Line 44: if (!CONFIG(PCIB_ENABLE)) { braces {} are not necessary for single statement blocks
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31813 )
Change subject: Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX) ......................................................................
Patch Set 1:
Not sure if this is the way to go. The original intention of IS_ENABLED(), as I understood it, was to avoid problems with undefined CONFIG_* macros. For instance in CPP, an undefined CONFIG_ would be true for an #if, and one defined to 0 would be true for an #ifdef. IS_ENABLED() solved that very nicely.
In C, we have other issues. I would always prefer a plain `CONFIG_...` in C, simply because it results in a compile time error when the config is undefined.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31813 )
Change subject: Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX) ......................................................................
Patch Set 1:
Not sure if this is the way to go. The original intention of IS_ENABLED(), as I understood it, was to avoid problems with undefined CONFIG_* macros. For instance in CPP, an undefined CONFIG_ would be true for an #if, and one defined to 0 would be true for an #ifdef. IS_ENABLED() solved that very nicely.
In C, we have other issues. I would always prefer a plain `CONFIG_...` in C, simply because it results in a compile time error when the config is undefined.
I mean... I'm not sure how useful it is, but as far as I understood it, the expected code style is to use IS_ENABLED() (and now CONFIG()) everywhere, for all boolean Kconfigs, in both preprocessor and C. That's what I've always been told in reviews, and that's what I've then started telling other people.
If we think it's crap we can start a bigger discussion about whether we want to change it if you want, but for now I'm pretty sure that's what we've been doing and what the vast majority of our code already conforms to, so I was just trying to eliminate the last few stragglers here.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31813 )
Change subject: Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX) ......................................................................
Patch Set 1: Code-Review+2
I guess I can still start a discussion if my concerns ever become an issue. Also, regarding the original intention, from the commit message of c0e16e7:
Long term plan is to remove our Kconfig hack to #define values to 0, and this helps.
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31813 )
Change subject: Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX) ......................................................................
Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few).
Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner jwerner@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/arch/arm/armv7/mmu.c M src/arch/x86/failover.ld M src/arch/x86/memlayout.ld M src/commonlib/storage/sdhci.c M src/cpu/amd/family_10h-family_15h/fidvid.c M src/cpu/amd/quadcore/amd_sibling.c M src/cpu/intel/hyperthreading/intel_sibling.c M src/device/device.c M src/drivers/intel/wifi/wifi.c M src/drivers/pc80/pc/keyboard.c M src/include/device/hypertransport_def.h M src/include/device/i2c_simple.h M src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c M src/mainboard/amd/olivehillplus/BiosCallOuts.c M src/mainboard/amd/torpedo/gpio.c M src/mainboard/bap/ode_e21XX/BiosCallOuts.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu2/BiosCallOuts.c M src/northbridge/amd/amdfam10/northbridge.c M src/northbridge/amd/pi/agesawrapper.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/nvidia/tegra124/bootblock.c M src/soc/nvidia/tegra210/bootblock.c M src/southbridge/amd/cimx/sb800/cfg.c M src/southbridge/amd/cimx/sb900/early.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/nvidia/ck804/ck804.h 31 files changed, 51 insertions(+), 51 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 14f5f7a..ce9d3fd 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -277,7 +277,7 @@ for (; (pte_t *)_ettb_subtables - table > 0; table += SUBTABLE_PTES) table[0] = ATTR_UNUSED;
- if (CONFIG_ARM_LPAE) { + if (CONFIG(ARM_LPAE)) { pte_t *const pgd_buff = (pte_t *)(_ttb + 16*KiB); pte_t *pmd = ttb_buff; int i; @@ -331,7 +331,7 @@ * See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected. */ write_ttbcr( - CONFIG_ARM_LPAE << 31 | /* EAE. 1:Enable LPAE */ + CONFIG(ARM_LPAE) << 31 |/* EAE. 1:Enable LPAE */ 0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */ );
diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index b32aa29..a9a5942 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -28,7 +28,7 @@ * boundary anyway, so no pad byte appears between _rom and _start. */ .bogus ROMLOC_MIN : { - . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); + . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(4); ROMLOC = .; } >rom = 0xff
@@ -50,10 +50,10 @@ * address gets applied. */ ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); + (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 0);
/* Post-check proper SIPI vector. */ - _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff), + _bogus = ASSERT(!CONFIG(SIPI_VECTOR_IN_ROM) || (ap_sipi_vector_in_rom == 0xff), "Address mismatch on AP_SIPI_VECTOR");
/DISCARD/ : { diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 8e073f2..cc72552 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -26,7 +26,7 @@ * conditionalize with macros. */ #if ENV_RAMSTAGE - RAMSTAGE(CONFIG_RAMBASE, (CONFIG_RELOCATABLE_RAMSTAGE ? 8M : + RAMSTAGE(CONFIG_RAMBASE, (CONFIG(RELOCATABLE_RAMSTAGE) ? 8M : CONFIG_RAMTOP - CONFIG_RAMBASE))
#elif ENV_ROMSTAGE diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 1370a91..5c85e99 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -30,9 +30,9 @@ #include <timer.h> #include <commonlib/stdlib.h>
-#define DMA_AVAILABLE ((CONFIG_SDHCI_ADMA_IN_BOOTBLOCK && ENV_BOOTBLOCK) \ - || (CONFIG_SDHCI_ADMA_IN_VERSTAGE && ENV_VERSTAGE) \ - || (CONFIG_SDHCI_ADMA_IN_ROMSTAGE && ENV_ROMSTAGE) \ +#define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \ + || (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_VERSTAGE) \ + || (CONFIG(SDHCI_ADMA_IN_ROMSTAGE) && ENV_ROMSTAGE) \ || ENV_POSTCAR || ENV_RAMSTAGE)
__weak void *dma_malloc(size_t length_in_bytes) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index db58f5d..579cae5 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -1084,7 +1084,7 @@ init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, -1, init_fidvid_bsp_stage1, &fv); + for_each_ap(bsp_apicid, CONFIG(SET_FIDVID_CORE0_ONLY), -1, init_fidvid_bsp_stage1, &fv); #endif
print_debug_fv("common_fid = ", fv.common_fid); diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index 000cb88..f9aba51 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -74,7 +74,7 @@ u32 siblings; u32 nb_cfg_54;
- u32 disable_siblings = !CONFIG_LOGICAL_CPUS; + u32 disable_siblings = !CONFIG(LOGICAL_CPUS);
get_option(&disable_siblings, "multi_core");
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index f2f28f6..e634f85 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -24,7 +24,7 @@ #endif
static int first_time = 1; -static int disable_siblings = !CONFIG_LOGICAL_CPUS; +static int disable_siblings = !CONFIG(LOGICAL_CPUS);
/* Return true if running thread does not have the smallest lapic ID * within a CPU core. diff --git a/src/device/device.c b/src/device/device.c index ae0dbdb..1b4255b 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -790,12 +790,12 @@ if (!vga) vga = vga_onboard;
- if (CONFIG_ONBOARD_VGA_IS_PRIMARY && vga_onboard) + if (CONFIG(ONBOARD_VGA_IS_PRIMARY) && vga_onboard) vga = vga_onboard;
/* If we prefer plugin VGA over chipset VGA, the chipset might want to know. */ - if (!CONFIG_ONBOARD_VGA_IS_PRIMARY && (vga != vga_onboard) && + if (!CONFIG(ONBOARD_VGA_IS_PRIMARY) && (vga != vga_onboard) && vga_onboard && vga_onboard->ops && vga_onboard->ops->disable) { printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n"); vga_onboard->ops->disable(vga_onboard); diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index d78b007..c0f665f 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -101,7 +101,7 @@ package_size = 1 + 1 + BYTES_PER_SAR_LIMIT; acpigen_write_package(package_size); acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI); - acpigen_write_dword(CONFIG_SAR_ENABLE); + acpigen_write_dword(CONFIG(SAR_ENABLE)); for (i = 0; i < BYTES_PER_SAR_LIMIT; i++) acpigen_write_byte(sar_limits.sar_limit[0][i]); acpigen_pop_len(); @@ -130,7 +130,7 @@ package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT; acpigen_write_package(package_size); acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI); - acpigen_write_dword(CONFIG_DSAR_ENABLE); + acpigen_write_dword(CONFIG(DSAR_ENABLE)); acpigen_write_dword(CONFIG_DSAR_SET_NUM); for (i = 1; i < NUM_SAR_LIMITS; i++) for (j = 0; j < BYTES_PER_SAR_LIMIT; j++) diff --git a/src/drivers/pc80/pc/keyboard.c b/src/drivers/pc80/pc/keyboard.c index 3849e73..bfd05c1 100644 --- a/src/drivers/pc80/pc/keyboard.c +++ b/src/drivers/pc80/pc/keyboard.c @@ -249,7 +249,7 @@ enum cb_err err; uint8_t aux_dev_detected;
- if (!CONFIG_DRIVERS_PS2_KEYBOARD) + if (!CONFIG(DRIVERS_PS2_KEYBOARD)) return 0;
if (acpi_is_wakeup_s3()) diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h index 4b340e8..ef9de2c 100644 --- a/src/include/device/hypertransport_def.h +++ b/src/include/device/hypertransport_def.h @@ -23,7 +23,7 @@ { bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); - return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + return need_offset && (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) || is_sb_ht_chain); }
diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h index dcde601..e3cc892 100644 --- a/src/include/device/i2c_simple.h +++ b/src/include/device/i2c_simple.h @@ -54,7 +54,7 @@ static inline int i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count) { - if (CONFIG_SOFTWARE_I2C) + if (CONFIG(SOFTWARE_I2C)) if (bus < SOFTWARE_I2C_MAX_BUS && software_i2c[bus]) return software_i2c_transfer(bus, segments, count);
diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c index c6e575d..af5d34e 100644 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c @@ -269,7 +269,7 @@ if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c index a6f4267..e3107b1 100644 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c @@ -253,7 +253,7 @@ FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index 4a8861c..51e3571 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -340,7 +340,7 @@ // // Enable/Disable OnBoard LAN // - if (!CONFIG_ONBOARD_LAN) + if (!CONFIG(ONBOARD_LAN)) { // 1 - DISABLED RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); @@ -358,7 +358,7 @@ // // Enable/Disable 1394 // - if (!CONFIG_ONBOARD_1394) + if (!CONFIG(ONBOARD_1394)) { // 1 - DISABLED // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off @@ -387,7 +387,7 @@ // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { // disable Onboard NEC USB3.0 controller - if (!CONFIG_ONBOARD_USB30) { + if (!CONFIG(ONBOARD_USB30)) { RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE @@ -401,7 +401,7 @@ // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE // GPIO07: BT_ON, 0 - OFF, 1 - ON // - if (!CONFIG_ONBOARD_BLUETOOTH) { + if (!CONFIG(ONBOARD_BLUETOOTH)) { //- if (SystemConfiguration.amdBlueTooth == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); //- } @@ -412,7 +412,7 @@ // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF // - if (!CONFIG_ONBOARD_WEBCAM) { + if (!CONFIG(ONBOARD_WEBCAM)) { //- if (SystemConfiguration.amdWebCam == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); //- } @@ -423,7 +423,7 @@ // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE // - if (!CONFIG_ONBOARD_TRAVIS) { + if (!CONFIG(ONBOARD_TRAVIS)) { //- if (SystemConfiguration.amdTravisCtrl == 0) { RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); //- } @@ -432,7 +432,7 @@ // // Disable Light Sensor if needed // - if (CONFIG_ONBOARD_LIGHTSENSOR) { + if (CONFIG(ONBOARD_LIGHTSENSOR)) { //- if (SystemConfiguration.amdLightSensor == 1) { RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); //- } diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 362b5ba..1d86d53 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -255,7 +255,7 @@ FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 79a54b5..e5e30e0 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -139,16 +139,16 @@ uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0); if (uart) - uart->enabled = CONFIG_APU1_PINMUX_UART_C; + uart->enabled = CONFIG(APU1_PINMUX_UART_C); if (gpio) - gpio->enabled = CONFIG_APU1_PINMUX_GPIO0; + gpio->enabled = CONFIG(APU1_PINMUX_GPIO0);
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1); if (uart) - uart->enabled = CONFIG_APU1_PINMUX_UART_D; + uart->enabled = CONFIG(APU1_PINMUX_UART_D); if (gpio) - gpio->enabled = CONFIG_APU1_PINMUX_GPIO1; + gpio->enabled = CONFIG(APU1_PINMUX_GPIO1); }
static void pnp_raw_resource(struct device *dev, u8 reg, u8 val) @@ -165,11 +165,11 @@ struct device *uart;
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); - if (uart && uart->enabled && CONFIG_UART_C_RS485) + if (uart && uart->enabled && CONFIG(UART_C_RS485)) pnp_raw_resource(uart, 0xf2, 0x12);
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); - if (uart && uart->enabled && CONFIG_UART_D_RS485) + if (uart && uart->enabled && CONFIG(UART_D_RS485)) pnp_raw_resource(uart, 0xf2, 0x12); }
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 8fc3d5a..535024a 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -69,7 +69,7 @@ FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 16b7bec..1d071c1 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -177,7 +177,7 @@ pci_write_config32(link->dev, link->cap + 0x14, busses);
if (mode == HT_ROUTE_FINAL) { - if (CONFIG_HT_CHAIN_DISTRIBUTE) + if (CONFIG(HT_CHAIN_DISTRIBUTE)) parent->subordinate = ALIGN_UP(link->subordinate, 8) - 1; else parent->subordinate = link->subordinate; @@ -1450,7 +1450,7 @@ siblings = 3; //quad core }
- disable_siblings = !CONFIG_LOGICAL_CPUS; + disable_siblings = !CONFIG(LOGICAL_CPUS); #if CONFIG(LOGICAL_CPUS) get_option(&disable_siblings, "multi_core"); #endif diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 28f2876..1cc7b7c 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -127,7 +127,7 @@
// Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow // the compiler to flag the error if CONFIG_GFXUMA is not set. - PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; + PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; PostParams->MemConfig.BottomIo = (UINT16) (CONFIG_BOTTOMIO_POSITION >> 24); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index ee656de..9c4f410 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -677,10 +677,10 @@ if (err == 0) gfx_set_init_done(1); /* Linux relies on VBT for panel info. */ - if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CALISTOGA"); } - if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { generate_fake_intel_oprom(&conf->gfx, dev, "$VBT LAKEPORT-G"); } } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 05b5777..be3d17a 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -284,7 +284,7 @@ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
/* clear self refresh status if check is disabled or not a resume */ - if (!CONFIG_CHECK_SLFRCS_ON_RESUME + if (!CONFIG(CHECK_SLFRCS_ON_RESUME) || sysinfo->boot_path != BOOT_PATH_RESUME) { MCHBAR8(SLFRCS) |= 3; } else { diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index b49165c..7465080 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -67,7 +67,7 @@ mainboard_config_superio();
/* USB is initialized in MRC if MRC is used. */ - if (CONFIG_USE_NATIVE_RAMINIT) { + if (CONFIG(USE_NATIVE_RAMINIT)) { early_usb_init(mainboard_usb_ports); }
diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 485dfd7..5295567 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -180,7 +180,7 @@
AMD_POST_PARAMS *PostParams = create_struct(&AmdParamStruct);
- PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; + PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; PostParams->MemConfig.BottomIo = (uint16_t) (CONFIG_BOTTOMIO_POSITION >> 24); diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 182fadb..c750304 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -64,7 +64,7 @@ pinmux_set_config(PINMUX_UART2_RTS_N_INDEX, PINMUX_UART2_RTS_N_FUNC_UB3);
- if (CONFIG_BOOTBLOCK_CONSOLE) { + if (CONFIG(BOOTBLOCK_CONSOLE)) { console_init(); exception_init(); } diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index 97ea1c9..96fb9b2 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -177,7 +177,7 @@
bootblock_mainboard_early_init();
- if (CONFIG_BOOTBLOCK_CONSOLE) { + if (CONFIG(BOOTBLOCK_CONSOLE)) { console_init(); exception_init(); printk(BIOS_INFO, "T210: Bootblock here\n"); diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 4487df3..b52918d 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -101,7 +101,7 @@ #endif /* LPC */ /* SuperIO hardware monitor register access */ - sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM; + sb_config->SioHwmPortEnable = CONFIG(SB_SUPERIO_HWM);
/* * GPP. default configure only enable port0 with 4 lanes, diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 1109290..5ebe47e 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -40,7 +40,7 @@ outb(0xEA, 0xCD6); data = inb(0xCD7); data &= !BIT0; - if (!CONFIG_PCIB_ENABLE) { + if (!CONFIG(PCIB_ENABLE)) { data |= BIT0; } outb(data, 0xCD7); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index eda16da..e9e4964 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -418,7 +418,7 @@
static void pch_set_acpi_mode(void) { - if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) { + if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index fe1d84a..f4464f3 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -433,7 +433,7 @@
static void pch_set_acpi_mode(void) { - if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) { + if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h index fc99d9a..5505691 100644 --- a/src/southbridge/nvidia/ck804/ck804.h +++ b/src/southbridge/nvidia/ck804/ck804.h @@ -24,7 +24,7 @@ #endif
#define CK804B_BUSN 0x80 -#define CK804B_DEVN_BASE (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY ? CK804_DEVN_BASE : 1) +#define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1)
#ifdef __PRE_RAM__ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);