[M] Change in coreboot[main]: mb/google/brox: Remove psys related implementation

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84397?usp=email )

(

6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/brox: Remove psys related implementation
......................................................................

mb/google/brox: Remove psys related implementation

psys is not an optimal solution for no/low battery boot. Hence remove
function and macros related to psys implementation.

BUG=b:335046538
BRANCH=None
TEST=Build and boot on brox board

Change-Id: I6c0e9561367b5846b00be27012f002dd7c299414
Signed-off-by: Sowmya Aralguppe 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84397
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Ashish Kumar Mishra 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
M src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
2 files changed, 0 insertions(+), 107 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Karthik Ramasubramanian: Looks good to me, approved
  Ashish Kumar Mishra: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
index 85c3c48..3cca344 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
@@ -12,9 +12,6 @@

WEAK_DEV_PTR(dptf_policy);

-#define SET_PSYSPL2(e, w) ((e) * (w) / 100)
-#define SET_PL2(e, w) ((e - 27) * (w) / 100)
-
 static bool get_sku_index(const struct cpu_power_limits *limits, size_t num_entries,
    				size_t *intel_idx, size_t *brox_idx)
 {
@@ -103,79 +100,3 @@
    	settings->pl1.min_power, settings->pl1.max_power, settings->pl2.min_power,
    	settings->pl2.max_power, soc_config->tdp_pl4);
 }
-
-/*
- * Psys calculations
- *
- * We use the following:
- *
- * For USB C charger (Max Power):
- * +-------------+-----+------+---------+-------+
- * | Max Power(W)| TDP | PL2  | PsysPL2 | PL3/4 |
- * +-------------+-----+------+---------+-------+
- * |     30      |  15 |  17  |   25    |  25   | <--- not working yet
- * |     45      |  15 |  26  |   38    |  38   |
- * |     60      |  15 |  35  |   51    |  51   |
- * |    110      |  15 |  55  |   94    |  96   |
- * +-------------+-----+------+---------+-------+
- */
-void variant_update_psys_power_limits(const struct cpu_power_limits *limits,
-				      const struct system_power_limits *sys_limits,
-				      size_t num_entries,
-				      const struct psys_config *config_psys)
-{
-	struct soc_power_limits_config *soc_config;
-	size_t intel_idx, brox_idx;
-	u16 volts_mv, current_ma;
-	enum usb_chg_type type;
-	u32 pl2;
-	u32 psyspl2 = 0;
-	u32 psyspl3 = 0;
-	u32 pl2_default;
-	config_t *conf;
-	u32 watts = 0;
-	int rv;
-
-	if (!num_entries)
-		return;
-
-	if (!get_sku_index(limits, num_entries, &intel_idx, &brox_idx))
-		return;
-
-	conf = config_of_soc();
-	soc_config = &conf->power_limits_config[intel_idx];
-
-	pl2_default = DIV_ROUND_UP(limits[brox_idx].pl2_max_power, MILLIWATTS_TO_WATTS);
-
-	/* Get AC adapter power */
-	rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
-
-	if (rv == 0 && type == USB_CHG_TYPE_PD) {
-		/* Detected USB-PD. Get max value of adapter */
-		watts = ((u32)current_ma * volts_mv) / 1000000;
-	}
-	/* If battery is present and has enough charge, add discharge rate */
-	if (CONFIG(EC_GOOGLE_CHROMEEC) &&
-		google_chromeec_is_battery_present_and_above_critical_threshold()) {
-		watts += 65;
-	}
-
-	/* We did not detect a battery or a Type-C charger */
-	if (watts == 0) {
-		return;
-	}
-
-	/* set psyspl2 to efficiency% of adapter rating */
-	psyspl2 = SET_PSYSPL2(config_psys->efficiency, watts);
-	psyspl3 = psyspl2;
-	if (watts > 60)
-		psyspl3 += 2;
-
-	/* Limit PL2 if the adapter is with lower capability */
-	pl2 = (psyspl2 > pl2_default) ? pl2_default : SET_PL2(config_psys->efficiency, watts);
-
-	/* now that we're done calculating, set everything */
-	soc_config->tdp_pl2_override = pl2;
-	soc_config->tdp_psyspl2 = psyspl2;
-	soc_config->tdp_psyspl3 = psyspl3;
-}
diff --git a/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
index ad8eb05..d04a793 100644
--- a/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
@@ -51,39 +51,11 @@
 struct system_power_limits {
    uint16_t mchid;
    u8 cpu_tdp;
-	/* PsysPL2 in Watts */
-	unsigned int psys_pl2_power;
-};
-
-struct psys_config {
-	/*
-	 * The efficiency of type-c chargers
-	 * For example, 'efficiency = 97' means setting 97% of max power to account for
-	 * cable loss and FET Rdson loss in the path from the source.
-	 */
-	unsigned int efficiency;
-
-	/* The maximum current maps to the Psys signal */
-	unsigned int psys_imax_ma;
-
-	/* The voltage of barrel jack */
-	unsigned int bj_volts_mv;
 };

/* Modify Power Limit devictree settings during ramstage */
 void variant_update_power_limits(const struct cpu_power_limits *limits,
    			 size_t num_entries);
-
-
-/*
- * Modify Power Limit and PsysPL devictree settings during ramstage.
- * Note, this function must be called in front of calling variant_update_power_limits.
- */
-void variant_update_psys_power_limits(const struct cpu_power_limits *limits,
-					const struct system_power_limits *sys_limits,
-					size_t num_entries,
-					const struct psys_config *config);
-
 void variant_init(void);
 void variant_finalize(void);