Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46781 )
Change subject: sb/intel/lynxpoint/acpi/lpc.asl: Simplify GPIOBASE resource ......................................................................
sb/intel/lynxpoint/acpi/lpc.asl: Simplify GPIOBASE resource
LynxPoint-LP handles GPIOs differently, and LynxPoint-H has the same GPIO kind as previous-generation PCHs, such as Cougar Point. Remove the unnecessary `_CRS` method and declare the GPIOBASE resource statically.
The preprocessor allows later ACPI deduplication to remain reproducible.
Change-Id: If771d5b6c3a1623da7d015ed50199877615409b2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/acpi/lpc.asl 1 file changed, 4 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46781/1
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 8f41e67..bdfd3e1 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -157,27 +157,13 @@ IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0xff)
- // GPIO region may be 128 bytes or 4096 bytes - IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR1) - }) - - Method (_CRS, 0, NotSerialized) - { +#if !CONFIG(INTEL_LYNXPOINT_LP) // LynxPoint-LP GPIO resources are defined in the // SerialIO GPIO device and LynxPoint-H GPIO resources // are defined here. - If (!\ISLP ()) { - CreateByteField (^RBUF, ^GPR1._LEN, R1LN) - CreateWordField (^RBUF, ^GPR1._MIN, R1MN) - CreateWordField (^RBUF, ^GPR1._MAX, R1MX) - - // Update GPIO region length - R1MN = DEFAULT_GPIOBASE - R1MX = DEFAULT_GPIOBASE - R1LN = DEFAULT_GPIOSIZE - } - Return (RBUF) - } + IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) +#endif + }) }
Device (RTC) // Real Time Clock
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46781
to look at the new patch set (#8).
Change subject: sb/intel/lynxpoint/acpi/lpc.asl: Simplify GPIOBASE resource ......................................................................
sb/intel/lynxpoint/acpi/lpc.asl: Simplify GPIOBASE resource
LynxPoint-LP handles GPIOs differently, and LynxPoint-H has the same GPIO kind as previous-generation PCHs, such as Cougar Point. Remove some unneeded logic from `_CRS` and declare the GPIOBASE resource statically.
The preprocessor allows later ACPI deduplication to remain reproducible.
Change-Id: If771d5b6c3a1623da7d015ed50199877615409b2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/acpi/lpc.asl 1 file changed, 6 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46781/8
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46781 )
Change subject: sb/intel/lynxpoint/acpi/lpc.asl: Simplify GPIOBASE resource ......................................................................
Patch Set 9: Code-Review+1
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46781 )
Change subject: sb/intel/lynxpoint/acpi/lpc.asl: Simplify GPIOBASE resource ......................................................................
Patch Set 9: Code-Review+2
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46781 )
Change subject: sb/intel/lynxpoint/acpi/lpc.asl: Simplify GPIOBASE resource ......................................................................
sb/intel/lynxpoint/acpi/lpc.asl: Simplify GPIOBASE resource
LynxPoint-LP handles GPIOs differently, and LynxPoint-H has the same GPIO kind as previous-generation PCHs, such as Cougar Point. Remove some unneeded logic from `_CRS` and declare the GPIOBASE resource statically.
The preprocessor allows later ACPI deduplication to remain reproducible.
Change-Id: If771d5b6c3a1623da7d015ed50199877615409b2 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46781 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/lynxpoint/acpi/lpc.asl 1 file changed, 6 insertions(+), 15 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 8f41e67..a823b70 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -157,25 +157,16 @@ IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0xff)
- // GPIO region may be 128 bytes or 4096 bytes - IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR1) +#if !CONFIG(INTEL_LYNXPOINT_LP) + // LynxPoint-LP GPIO resources are defined in the + // SerialIO GPIO device and LynxPoint-H GPIO resources + // are defined here. + IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) +#endif })
Method (_CRS, 0, NotSerialized) { - // LynxPoint-LP GPIO resources are defined in the - // SerialIO GPIO device and LynxPoint-H GPIO resources - // are defined here. - If (!\ISLP ()) { - CreateByteField (^RBUF, ^GPR1._LEN, R1LN) - CreateWordField (^RBUF, ^GPR1._MIN, R1MN) - CreateWordField (^RBUF, ^GPR1._MAX, R1MX) - - // Update GPIO region length - R1MN = DEFAULT_GPIOBASE - R1MX = DEFAULT_GPIOBASE - R1LN = DEFAULT_GPIOSIZE - } Return (RBUF) } }
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)