Change in coreboot[master]: mb/google/brya: Enable S0ix

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51526 )

Change subject: mb/google/brya: Enable S0ix
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mb/google/brya: Enable S0ix

This change enables S0ix for brya platform.

BUG=b:181843816
TEST=Built image and booted to kernel.

Change-Id: Idc6f7fce9779ef4458375becebf5dc65b228abeb
Signed-off-by: Sugnan Prabhu S 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51526
Reviewed-by: EricR Lai 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/brya/variants/baseboard/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  EricR Lai: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index 33be862..3155d04 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -14,6 +14,9 @@
    # EC memory map range is 0x900-0x9ff
    register "gen3_dec" = "0x00fc0901"

+        # S0ix enable
+        register "s0ix_enable" = "1"
+
    # This disabled autonomous GPIO power management, otherwise
    # old cr50 FW only supports short pulses; need to clarify
    # the minimum PCH IRQ pulse width with Intel, b/180111628