Change in coreboot[master]: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT

[Michał Żygowski (Code Review)]

Attention is currently required from: Angel Pons, Patrick Rudolph.
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59523 )

Change subject: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT
......................................................................

nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT

Initialize the DPR register and check if SCLEAN needs to be run.
Allows to reliably boot the platform if ungraceful shutdown occured or
the memory controller has been locked by TXT.

TEST=Dell OptiPlex 9010 with Intel TXT enabled boots successfully
after 4s power button override or power cable unplug when SENTER was
executed. Successfully boot QubesOS 4.0 with TBoot v1.8.2

Signed-off-by: Michał Żygowski 
Change-Id: I4b912f121593fa55c11813262f09be1a1055e950
---
M src/northbridge/intel/sandybridge/romstage.c
1 file changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/59523/1

diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index d6e7ee9..15608cf 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -10,6 +10,9 @@
 #include <device/pci_def.h>
 #include <device/device.h>
 #include <northbridge/intel/sandybridge/chip.h>
+#include <security/intel/txt/txt.h>
+#include <security/intel/txt/txt_platform.h>
+#include <security/intel/txt/txt_register.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <elog.h>
@@ -22,6 +25,18 @@
 {
 }

+#if CONFIG(INTEL_TXT)
+static void configure_dpr(void)
+{
+	union dpr_register dpr = txt_get_chipset_dpr();
+
+	dpr.lock = 1;
+	dpr.epm = 1;
+	dpr.size = CONFIG_INTEL_TXT_DPR_SIZE; /* 3 MiB should be enough */
+	pci_write_config32(HOST_BRIDGE, DPR, dpr.raw);
+}
+#endif
+
 static void early_pch_reset_pmcon(void)
 {
    /* Reset RTC power status */
@@ -60,6 +75,11 @@

post_code(0x39);

+#if CONFIG(INTEL_TXT)
+	configure_dpr();
+	intel_txt_romstage_init();
+#endif
+
    perform_raminit(s3resume);

post_code(0x3b);