Attention is currently required from: Jérémy Compostella, Nico Huber.
Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83064?usp=email )
Change subject: cpu/x86/smm: Add save state ops for different save states ......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS4:
Hey Arthur, Is this currently being worked?
I not currently. The series probably needs to be updated to account for the fact that synchronous SMI can not be differentiated in qemu. Other than that I need to address the comments.
File src/cpu/x86/smm/legacy_save_state.c:
https://review.coreboot.org/c/coreboot/+/83064/comment/0fae86b9_e63ca5e4?usp... : PS4, Line 89: }
This looks like it would go wrong 1 out of 512 times on a dual core / socket system. Is there no way to detect the AMPC or did just nobody look into it?
There is apparently but it depends on the hardware whether the 'I/O State Field' exists. "Processors that have an SMM revision ID of 30004H or higher have the incremental state information described below."
I think using CPU registers for this interface was a mistake. Finding which cpu initiated the synchronous SMI does not always go right iirc (I think the workaround is to try multiple times). There used to be a SMIF in GNVS for this purpose.