Kevin Chiu (Kevin.Chiu@quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17779
-gerrit
commit de8a725ebdd45b174dcf1751ad297a498d13a763 Author: Kevin Chiu Kevin.Chiu@quantatw.com Date: Fri Dec 9 11:42:05 2016 +0800
google/pyro: Set PL2 override to 15000mW
This patch sets PL2 override value to 15W in RAPL registers and sets DPTF PL2 Max to 15W
BUG=none BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ibadf0fa442f556d018c249b1cf88e29c4d57c97f Signed-off-by: Kevin Chiu Kevin.Chiu@quantatw.com --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 2 ++ src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index b5e050e..bc06bbb 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -53,6 +53,8 @@ chip soc/intel/apollolake # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. register "tdp_pl1_override_mw" = "12000" + # Set RAPL PL2 to 15W. + register "tdp_pl2_override_mw" = "15000"
# Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl index 7e2f31c..f14999c 100644 --- a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl @@ -81,7 +81,7 @@ Name (MPPC, Package () Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ 6000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ + 15000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 1000 /* StepSize */
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Kevin Chiu