[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PLL and Clock init support

[Guangjie Song (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu.

Guangjie Song has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84495?usp=email )

Change subject: soc/mediatek/mt8196: Add PLL and Clock init support
......................................................................

Patch Set 26:

(1 comment)

File src/soc/mediatek/mt8196/pll.c:

https://review.coreboot.org/c/coreboot/+/84495/comment/85bf3d2d_47c3f29e?usp... :
PS13, Line 1196: 30
> @[e-mail]  […]

"cg_idx" is pre-assigned and has a 1:1 mapping relationship with the clock control register. Values of cg_idx beyond 30 are not mapped to specific clock control registers, so they have no practical significance and therefore no macros are defined to match them.