[XL] Change in coreboot[main]: skl/kbl mainboards: Move PCIe related settings into their device scope
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83373?usp=email )
Change subject: skl/kbl mainboards: Move PCIe related settings into their device scope ......................................................................
skl/kbl mainboards: Move PCIe related settings into their device scope
Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373 Reviewed-by: Eric Lai ericllai@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Frans Hendriks fhendriks@eltan.com Reviewed-by: Matt DeVillier matt.devillier@gmail.com Reviewed-by: Erik van den Bogaert ebogaert@eltan.com Reviewed-by: Jonathon Hall jonathon.hall@puri.sm --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 25 files changed, 493 insertions(+), 637 deletions(-)
Approvals: Eric Lai: Looks good to me, but someone else must approve Frans Hendriks: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved Erik van den Bogaert: Looks good to me, but someone else must approve build bot (Jenkins): Verified Jonathon Hall: Looks good to me, but someone else must approve
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 3ffc00f..a33ee18 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -39,29 +39,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s
- # Enable Root Ports 3, 4 and 9 - register "PcieRpEnable[2]" = "1" # Ethernet controller - register "PcieRpClkReqSupport[2]" = "1" - register "PcieRpClkReqNumber[2]" = "0" - register "PcieRpClkSrcNumber[2]" = "0" - register "PcieRpAdvancedErrorReporting[2]" = "1" - register "PcieRpLtrEnable[2]" = "1" - - register "PcieRpEnable[3]" = "1" # Wireless controller - register "PcieRpClkReqSupport[3]" = "1" - register "PcieRpClkReqNumber[3]" = "1" - register "PcieRpClkSrcNumber[3]" = "1" - register "PcieRpAdvancedErrorReporting[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" - - register "PcieRpEnable[8]" = "1" # NVMe controller - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "4" - register "PcieRpClkSrcNumber[8]" = "4" - register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - - # PL1 override 25W # PL2 override 44W register "power_limits_config" = "{ @@ -110,9 +87,33 @@ [2] = 1, }" end - device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp9 on end + device ref pcie_rp3 on + # Ethernet controller + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqNumber[2]" = "0" + register "PcieRpClkSrcNumber[2]" = "0" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + end + device ref pcie_rp4 on + # Wireless controller + register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + end + device ref pcie_rp9 on + # NVMe controller + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + register "PcieRpClkSrcNumber[8]" = "4" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS"
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 763a380..7330862 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -111,57 +111,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
- # Enable Root ports. - # PCIE Port 1 disabled - # PCIE Port 2 disabled - - # PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard - register "PcieRpEnable[2]" = "1" - # Disable CLKREQ# - register "PcieRpClkReqSupport[2]" = "0" - # Set MaxPayload to 256 bytes - register "PcieRpMaxPayload[2]" = "RpMaxPayload_256" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[2]" = "1" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[2]" = "1" - # Disable Aspm - register "pcie_rp_aspm[2]" = "AspmDisabled" - - # PCIE Port 4 disabled - # PCIE Port 5 x1 -> MODULE i219 - - # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard - register "PcieRpEnable[5]" = "1" - register "PcieRpClkReqSupport[5]" = "0" - # Set MaxPayload to 256 bytes - register "PcieRpMaxPayload[5]" = "RpMaxPayload_256" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[5]" = "1" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[5]" = "1" - # Disable Aspm - register "pcie_rp_aspm[5]" = "AspmDisabled" - - # PCIE Port 7 Disabled - # PCIE Port 8 Disabled - - # PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA - register "PcieRpEnable[8]" = "1" - # Disable CLKREQ# - register "PcieRpClkReqSupport[8]" = "0" - # Use Hot Plug subsystem - register "PcieRpHotPlug[8]" = "1" - # Set MaxPayload to 256 bytes - register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[8]" = "1" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[8]" = "1" - # Disable Aspm - register "pcie_rp_aspm[8]" = "AspmDisabled" - - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, @@ -205,9 +154,37 @@ register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "1" end - device ref pcie_rp3 on end # x1 baseboard WWAN - device ref pcie_rp6 on end # x1 baseboard i210 - device ref pcie_rp9 on end # x4 FPGA + device ref pcie_rp3 on + # x1 baseboard WWAN + # PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "0" + register "PcieRpMaxPayload[2]" = "RpMaxPayload_256" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "pcie_rp_aspm[2]" = "AspmDisabled" + end + device ref pcie_rp6 on + # x1 baseboard i210 + # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "0" + register "PcieRpMaxPayload[5]" = "RpMaxPayload_256" + register "PcieRpLtrEnable[5]" = "1" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "pcie_rp_aspm[5]" = "AspmDisabled" + end + device ref pcie_rp9 on + # x4 FPGA + # PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "0" + register "PcieRpHotPlug[8]" = "1" + register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "pcie_rp_aspm[8]" = "AspmDisabled" + end device ref uart0 on end device ref emmc on end device ref lpc_espi on diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 38d0742..db843f5 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -116,25 +116,6 @@ .dc_loadline = 430, }"
- # Enable Root port 1 with SRCCLKREQ1# - register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" - register "PcieRpHotPlug[0]" = "1" - #RP 1 uses CLK SRC 1 - register "PcieRpClkSrcNumber[0]" = "1" - - # Enable Root port 5 with SRCCLKREQ4# - register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqNumber[4]" = "4" - register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" - #RP 5 uses CLK SRC 4 - register "PcieRpClkSrcNumber[4]" = "4" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -355,12 +336,26 @@ end end # I2C #4 device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpHotPlug[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end end - device ref pcie_rp5 on end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "4" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "4" + end device ref uart0 on end device ref gspi0 on chip drivers/spi/acpi diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 9458c81..25b8d9f 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -146,83 +146,6 @@ .dc_loadline = 310, }"
- # Enable Root port 3(x1) for LAN. - register "PcieRpEnable[2]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[2]" = "1" - # RP 3 uses SRCCLKREQ0# - register "PcieRpClkReqNumber[2]" = "0" - # RP 3, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[2]" = "1" - # RP 3, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[2]" = "1" - # RP 3 uses CLK SRC 0 - register "PcieRpClkSrcNumber[2]" = "0" - - # Enable Root port 4(x1) for WLAN. - register "PcieRpEnable[3]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[3]" = "1" - # RP 4 uses SRCCLKREQ5# - register "PcieRpClkReqNumber[3]" = "5" - # RP 4, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[3]" = "1" - # RP 4, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[3]" = "1" - # RP 4 uses CLK SRC 5 - register "PcieRpClkSrcNumber[3]" = "5" - - # Enable Root port 5(x4) for NVMe. - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[4]" = "1" - # RP 5 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[4]" = "1" - # RP 5, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" - # RP 5, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[4]" = "1" - # RP 5 uses CLK SRC 1 - register "PcieRpClkSrcNumber[4]" = "1" - - # Enable Root port 9 for BtoB. - register "PcieRpEnable[8]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[8]" = "1" - # RP 9 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[8]" = "2" - # RP 9, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[8]" = "1" - # RP 9, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses CLK SRC 2 - register "PcieRpClkSrcNumber[8]" = "2" - - # Enable Root port 11 for BtoB. - register "PcieRpEnable[10]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[10]" = "1" - # RP 11 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[10]" = "2" - # RP 11, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[10]" = "1" - # RP 11, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[10]" = "1" - # RP 11 uses CLK SRC 2 - register "PcieRpClkSrcNumber[10]" = "2" - - # Enable Root port 12 for BtoB. - register "PcieRpEnable[11]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[11]" = "1" - # RP 12 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[11]" = "2" - # RP 12, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[11]" = "1" - # RP 12, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[11]" = "1" - # RP 12 uses CLK SRC 2 - register "PcieRpClkSrcNumber[11]" = "2"
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM @@ -368,6 +291,13 @@ device ref pcie_rp1 on end device ref pcie_rp3 on # LAN, will be swapped to port 1 by FSP + # x1 + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqNumber[2]" = "0" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpClkSrcNumber[2]" = "0" chip drivers/net register "customized_leds" = "0x0fa5" register "wake" = "GPE0_PCI_EXP" @@ -376,23 +306,57 @@ end end device ref pcie_rp4 on - # WLAN + # x1 WLAN + register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "5" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "5" chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end end - device ref pcie_rp5 on end # NVMe + device ref pcie_rp5 on + # x4 NVMe + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "1" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "1" + end device ref pcie_rp9 on # 2nd LAN + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "2" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "2" chip drivers/net register "customized_leds" = "0x0fa5" register "device_index" = "1" device pci 00.0 on end end end - device ref pcie_rp11 on end - device ref pcie_rp12 on end + device ref pcie_rp11 on + register "PcieRpEnable[10]" = "1" + register "PcieRpClkReqSupport[10]" = "1" + register "PcieRpClkReqNumber[10]" = "2" + register "PcieRpAdvancedErrorReporting[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + register "PcieRpClkSrcNumber[10]" = "2" + end + device ref pcie_rp12 on + register "PcieRpEnable[11]" = "1" + register "PcieRpClkReqSupport[11]" = "1" + register "PcieRpClkReqNumber[11]" = "2" + register "PcieRpAdvancedErrorReporting[11]" = "1" + register "PcieRpLtrEnable[11]" = "1" + register "PcieRpClkSrcNumber[11]" = "2" + end device ref uart0 on end device ref gspi0 on chip drivers/spi/acpi diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 3da4f0e..649b5c1 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -1,47 +1,5 @@ chip soc/intel/skylake
- # Enable Root port 7(x1) for TPU1 - register "PcieRpEnable[6]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[6]" = "1" - # RP 7 uses SRCCLKREQ4# - register "PcieRpClkReqNumber[6]" = "4" - # RP 7, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[6]" = "1" - # RP 7, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[6]" = "1" - # RP 7 uses CLK SRC 4 - register "PcieRpClkSrcNumber[6]" = "4" - - # Enable Root port 8(x1) for TPU0 - register "PcieRpEnable[7]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[7]" = "1" - # RP 8 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[7]" = "2" - # RP 8, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[7]" = "1" - # RP 8, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[7]" = "1" - # RP 8 uses CLK SRC 2 - register "PcieRpClkSrcNumber[7]" = "2" - - # Enable Root port 9(x4) for i350 LAN - register "PcieRpEnable[8]" = "1" - # Disable CLKREQ# - register "PcieRpClkReqSupport[8]" = "0" - # RP 9, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[8]" = "1" - # RP 9, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses CLK SRC 2 - register "PcieRpClkSrcNumber[8]" = "2" - - # These are part of Root port 9(x4) - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # TPU register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # None @@ -159,11 +117,40 @@ device i2c 13 on end end end - device ref pcie_rp7 on end # TPU1 - device ref pcie_rp8 on end # TPU0 - device ref pcie_rp9 on end # POE LAN - device ref pcie_rp10 off end - device ref pcie_rp11 off end - device ref pcie_rp12 off end + device ref pcie_rp7 on + # x1 TPU1 + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "4" + register "PcieRpAdvancedErrorReporting[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieRpClkSrcNumber[6]" = "4" + end + device ref pcie_rp8 on + # x1 TPU0 + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqNumber[7]" = "2" + register "PcieRpAdvancedErrorReporting[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieRpClkSrcNumber[7]" = "2" + end + device ref pcie_rp9 on + # x4 i350 LAN + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "0" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "2" + end + device ref pcie_rp10 off + register "PcieRpEnable[9]" = "0" + end + device ref pcie_rp11 off + register "PcieRpEnable[10]" = "0" + end + device ref pcie_rp12 off + register "PcieRpEnable[11]" = "0" + end end end diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 88b7fbc..2d2e13c 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -41,13 +41,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 4s register "PmConfigSlpAMinAssert" = "3" # 2s
- # Enable Root port 1 - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -85,6 +78,9 @@ device ref uart2 on end device ref i2c4 on end device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW0_16" device pci 00.0 on end diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 85a1e23a..48b9a920 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -126,14 +126,6 @@ .dc_loadline = 425, }"
- # PCIe Root port 1 with SRCCLKREQ1# (WLAN) - register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkSrcNumber[0]" = "1" - register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -326,6 +318,13 @@ end end device ref pcie_rp1 on + # WLAN + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW1_07" # GPP_B7 device pci 00.0 on end diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index c44b380..17eee30 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -111,19 +111,6 @@ .dc_loadline = 420, }"
- # Enable Root port 1. - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" - # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" - # RP 1, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[0]" = "1" - # RP 1 uses CLK SRC 1 - register "PcieRpClkSrcNumber[0]" = "1" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -342,6 +329,12 @@ end device ref i2c4 on end device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" device pci 00.0 on end diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 43c1b4b..b970077 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -119,48 +119,6 @@ .dc_loadline = 310, }"
- # Root port 4 (x1) - # PcieRpEnable: Enable root port - # PcieRpClkReqSupport: Enable CLKREQ# - # PcieRpClkReqNumber: Uses SRCCLKREQ1# - # PcieRpClkSrcNumber: Uses 1 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting - # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism - register "PcieRpEnable[3]" = "1" - register "PcieRpClkReqSupport[3]" = "1" - register "PcieRpClkReqNumber[3]" = "1" - register "PcieRpClkSrcNumber[3]" = "1" - register "PcieRpAdvancedErrorReporting[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" - - # Root port 5 (x4) - # PcieRpEnable: Enable root port - # PcieRpClkReqSupport: Enable CLKREQ# - # PcieRpClkReqNumber: Uses SRCCLKREQ3# - # PcieRpClkSrcNumber: Uses 3 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting - # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism - register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqNumber[4]" = "3" - register "PcieRpClkSrcNumber[4]" = "3" - register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" - - # Root port 9 (x2) - # PcieRpEnable: Enable root port - # PcieRpClkReqSupport: Enable CLKREQ# - # PcieRpClkReqNumber: Uses SRCCLKREQ2# - # PcieRpClkSrcNumber: Uses 2 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting - # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "2" - register "PcieRpClkSrcNumber[8]" = "2" - register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - # Touchscreen register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
@@ -419,16 +377,39 @@ device ref pcie_rp2 off end device ref pcie_rp3 off end device ref pcie_rp4 on + # x1 + register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22 device pci 00.0 on end end end - device ref pcie_rp5 on end + device ref pcie_rp5 on + # x4 + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + end device ref pcie_rp6 off end device ref pcie_rp7 off end device ref pcie_rp8 off end - device ref pcie_rp9 on end + device ref pcie_rp9 on + # x2 + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "2" + register "PcieRpClkSrcNumber[8]" = "2" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + end device ref pcie_rp10 off end device ref pcie_rp11 off end device ref pcie_rp12 off end diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 5d31208..92d72f8 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -129,19 +129,6 @@ .dc_loadline = 420, }"
- # Enable Root port 1. - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" - # RP 1 uses CLK SRC 1 - register "PcieRpClkSrcNumber[0]" = "1" - # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" - # RP 1, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[0]" = "1" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -380,6 +367,12 @@ end end device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" device pci 00.0 on end diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 9853f49..27b2f0b 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -119,28 +119,6 @@ .dc_loadline = 430, }"
- # PCIe Root port 1 with SRCCLKREQ1# - register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkSrcNumber[0]" = "1" - register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" - - # Root port 9 (x2) - # PcieRpEnable: Enable root port - # PcieRpClkReqSupport: Enable CLKREQ# - # PcieRpClkReqNumber: Uses SRCCLKREQ2# - # PcieRpClkSrcNumber: Uses 3 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting - # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "2" - register "PcieRpClkSrcNumber[8]" = "3" - register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -354,6 +332,12 @@ end end device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW2_01" device pci 00.0 on end @@ -366,7 +350,15 @@ device ref pcie_rp6 off end device ref pcie_rp7 off end device ref pcie_rp8 off end - device ref pcie_rp9 on end + device ref pcie_rp9 on + # x2 + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "2" + register "PcieRpClkSrcNumber[8]" = "3" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + end device ref pcie_rp10 off end device ref pcie_rp11 off end device ref pcie_rp12 off end diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index fa57537..8c8eb7f 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -118,19 +118,6 @@ .dc_loadline = 430, }"
- # Enable Root port 1. - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" - # RP 1 uses CLK SRC 1 - register "PcieRpClkSrcNumber[0]" = "1" - # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" - # RP 1, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[0]" = "1" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -339,6 +326,12 @@ end device ref i2c4 off end device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" # GPP_B0 device pci 00.0 on end diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index d7dea15..5cb0f7d 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -120,19 +120,6 @@ .dc_loadline = 420, }"
- # Enable Root port 1. - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" - # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" - # RP 1, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[0]" = "1" - # RP 1 uses CLK SRC 1 - register "PcieRpClkSrcNumber[0]" = "1" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -325,6 +312,12 @@ end device ref i2c4 on end device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 9d4c0d9..20ea0c1 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -4,43 +4,6 @@ register "DspEnable" = "0" register "ScsEmmcHs400Enabled" = "0"
- # Enable PCIE slot - register "PcieRpEnable[5]" = "1" - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1 - # RP6, uses CLK SRC 1 - register "PcieRpClkSrcNumber[5]" = "1" - - register "PcieRpEnable[6]" = "1" - register "PcieRpClkReqSupport[6]" = "1" - register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2 - # RP7, uses CLK SRC 2 - register "PcieRpClkSrcNumber[6]" = "2" - - register "PcieRpEnable[7]" = "1" - register "PcieRpClkReqSupport[7]" = "1" - register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 - # RP8, uses CLK SRC 3 - register "PcieRpClkSrcNumber[7]" = "3" - - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - # RP9, uses CLK SRC 4 - register "PcieRpClkSrcNumber[8]" = "4" - - register "PcieRpEnable[13]" = "1" - register "PcieRpClkReqSupport[13]" = "1" - register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5 - # RP14, uses CLK SRC 5 - register "PcieRpClkSrcNumber[13]" = "5" - - register "PcieRpEnable[16]" = "1" - register "PcieRpClkReqSupport[16]" = "1" - register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7 - # RP17, uses CLK SRC 7 - register "PcieRpClkSrcNumber[16]" = "7" - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -111,6 +74,42 @@ }" end device ref i2c4 off end + device ref pcie_rp6 on + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "1" + register "PcieRpClkSrcNumber[5]" = "1" + end + device ref pcie_rp7 on + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "2" + register "PcieRpClkSrcNumber[6]" = "2" + end + device ref pcie_rp8 on + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqNumber[7]" = "3" + register "PcieRpClkSrcNumber[7]" = "3" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + register "PcieRpClkSrcNumber[8]" = "4" + end + device ref pcie_rp14 on + register "PcieRpEnable[13]" = "1" + register "PcieRpClkReqSupport[13]" = "1" + register "PcieRpClkReqNumber[13]" = "5" + register "PcieRpClkSrcNumber[13]" = "5" + end + device ref pcie_rp17 on + register "PcieRpEnable[16]" = "1" + register "PcieRpClkReqSupport[16]" = "1" + register "PcieRpClkReqNumber[16]" = "7" + register "PcieRpClkSrcNumber[16]" = "7" + end device ref emmc off end device ref sdxc off end device ref hda on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 7de1454..6bca121 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -33,44 +33,6 @@ .voltage_limit = 1520 }"
- # Enable Root ports. - # PCIE Port 1 x4 -> SLOT1 - register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "2" - # RP1, uses CLK SRC 2 - register "PcieRpClkSrcNumber[0]" = "2" - - # PCIE Port 5 x1 -> SLOT2/LAN - register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqNumber[4]" = "3" - # RP5, uses CLK SRC 3 - register "PcieRpClkSrcNumber[4]" = "3" - - # PCIE Port 6 x1 -> SLOT3 - register "PcieRpEnable[5]" = "1" - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqNumber[5]" = "1" - # RP6, uses CLK SRC 1 - register "PcieRpClkSrcNumber[5]" = "1" - - # PCIE Port 7 Disabled - # PCIE Port 8 Disabled - # PCIE Port 9 x1 -> WLAN - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "5" - # RP9, uses CLK SRC 5 - register "PcieRpClkSrcNumber[8]" = "5" - - # PCIE Port 10 x1 -> WiGig - register "PcieRpEnable[9]" = "1" - register "PcieRpClkReqSupport[9]" = "1" - register "PcieRpClkReqNumber[9]" = "4" - # RP10, uses CLK SRC 4 - register "PcieRpClkSrcNumber[9]" = "4" - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -113,11 +75,41 @@ end device ref imgu on end device ref cio on end - device ref pcie_rp1 on end # x4 SLOT1 - device ref pcie_rp5 on end # x1 SLOT2/LAN - device ref pcie_rp6 on end # x1 SLOT3 - device ref pcie_rp9 on end # x1 WLAN - device ref pcie_rp10 on end # x1 WIGIG + device ref pcie_rp1 on + # PCIE x4 -> SLOT1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "2" + register "PcieRpClkSrcNumber[0]" = "2" + end + device ref pcie_rp5 on + # PCIE x1 -> SLOT2/LAN + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + end + device ref pcie_rp6 on + # PCIE x1 -> SLOT3 + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "1" + register "PcieRpClkSrcNumber[5]" = "1" + end + device ref pcie_rp9 on + # PCIE x1 -> WLAN + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" + end + device ref pcie_rp10 on + # PCIE x1 -> WiGig + register "PcieRpEnable[9]" = "1" + register "PcieRpClkReqSupport[9]" = "1" + register "PcieRpClkReqNumber[9]" = "4" + register "PcieRpClkSrcNumber[9]" = "4" + end device ref lpc_espi on # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen2_dec" = "0x000c0201" diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 99963bf..c4f8d46 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -72,39 +72,6 @@ .voltage_limit = 0 }"
- # Enable Root ports. - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[8]" = "1" - - # Enable CLKREQ# - register "PcieRpClkReqSupport[2]" = "1" - register "PcieRpClkReqSupport[3]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - - # RP 3 uses SRCCLKREQ5# - register "PcieRpClkReqNumber[2]" = "5" - register "PcieRpClkReqNumber[3]" = "2" - register "PcieRpClkReqNumber[4]" = "3" - register "PcieRpClkReqNumber[5]" = "4" - register "PcieRpClkReqNumber[8]" = "1" - - # RP 3 uses CLK SRC 5# - register "PcieRpClkSrcNumber[2]" = "5" - # RP 4 uses CLK SRC 2# - register "PcieRpClkSrcNumber[3]" = "2" - # RP 5 uses CLK SRC 3# - register "PcieRpClkSrcNumber[4]" = "3" - # RP 6 uses CLK SRC 4# - register "PcieRpClkSrcNumber[5]" = "4" - # RP 9 uses CLK SRC 1# - register "PcieRpClkSrcNumber[8]" = "1" - - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -156,10 +123,36 @@ [2] = 1, }" end - device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp5 on end - device ref pcie_rp6 on end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqNumber[2]" = "5" + register "PcieRpClkSrcNumber[2]" = "5" + end + device ref pcie_rp4 on + register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "2" + register "PcieRpClkSrcNumber[3]" = "2" + end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + end + device ref pcie_rp6 on + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "4" + register "PcieRpClkSrcNumber[5]" = "4" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "1" + end device ref lpc_espi on # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen2_dec" = "0x000c0201" diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index eb13212..96bd56b 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -75,24 +75,6 @@ .voltage_limit = 0 }"
- # Enable Root port. - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[16]" = "1" - - # Enable CLKREQ# - register "PcieRpClkReqSupport[3]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqSupport[16]" = "1" - - # SRCCLKREQ# - register "PcieRpClkReqNumber[3]" = "2" - register "PcieRpClkReqNumber[4]" = "1" - register "PcieRpClkReqNumber[8]" = "6" - register "PcieRpClkReqNumber[16]" = "7" - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -165,8 +147,26 @@ device ref i2c4 off end device ref pcie_rp1 off end device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp5 on end + device ref pcie_rp4 on + register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "2" + end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "1" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "6" + end + device ref pcie_rp17 on + register "PcieRpEnable[16]" = "1" + register "PcieRpClkReqSupport[16]" = "1" + register "PcieRpClkReqNumber[16]" = "7" + end device ref emmc off end device ref sdxc off end device ref lpc_espi on diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 6e08059..458f559 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -103,17 +103,6 @@ .voltage_limit = 1520, }"
- # Enable Root port 1 and 5. - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkReqNumber[4]" = "2" - - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI @@ -221,12 +210,19 @@ end end device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW0_16" device pci 00.0 on end end end - device ref pcie_rp5 on end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "2" + end device ref uart0 on end device ref emmc on end device ref sdxc on end diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index c92377a..968e2a6 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -98,28 +98,6 @@ .voltage_limit = 1520, }"
- # Enable x1 slot - register "PcieRpEnable[7]" = "1" - register "PcieRpClkReqSupport[7]" = "1" - register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 - - # Enable x4 slot - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - - # Enable Root port 6 and 13. - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[12]" = "1" - - # Enable CLKREQ# - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqSupport[12]" = "1" - - # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[5]" = "0" - register "PcieRpClkReqNumber[12]" = "1" - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI @@ -207,6 +185,28 @@ device ref i2c5 on end device ref i2c4 on end device ref pcie_rp1 on end + device ref pcie_rp6 on + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "0" + end + device ref pcie_rp8 on + # x1 + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqNumber[7]" = "3" + end + device ref pcie_rp9 on + # x4 + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + end + device ref pcie_rp13 on + register "PcieRpEnable[12]" = "1" + register "PcieRpClkReqSupport[12]" = "1" + register "PcieRpClkReqNumber[12]" = "1" + end device ref uart0 on end device ref uart1 on end device ref gspi0 on end diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb index b6b3574..9cf710f 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -1,13 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/skylake - # Enable Root port 1..4 (COMe 4..7), 12 (COMe 3) - register "PcieRpEnable[ 0]" = "1" - register "PcieRpEnable[ 1]" = "1" - register "PcieRpEnable[ 2]" = "1" - register "PcieRpEnable[ 3]" = "1" - register "PcieRpEnable[11]" = "1" - device domain 0 on device ref south_xhci on register "usb2_ports" = "{ @@ -27,11 +20,26 @@ device ref sata on register "SataPortsEnable[3]" = "1" end - device ref pcie_rp1 on end - device ref pcie_rp2 on end - device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp12 on end + device ref pcie_rp1 on + # COMe 4 + register "PcieRpEnable[0]" = "1" + end + device ref pcie_rp2 on + # COMe 5 + register "PcieRpEnable[1]" = "1" + end + device ref pcie_rp3 on + # COMe 6 + register "PcieRpEnable[2]" = "1" + end + device ref pcie_rp4 on + # COMe 7 + register "PcieRpEnable[3]" = "1" + end + device ref pcie_rp12 on + # COMe 3 + register "PcieRpEnable[11]" = "1" + end device ref smbus on chip drivers/i2c/nct7802y register "peci[0]" = "{ PECI_DOMAIN_0, 100 }" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 2ebc6702..9599cec 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -97,21 +97,7 @@ .voltage_limit = 1520, }"
- register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpClkSrcNumber[0]" = "0" - register "PcieRpClkSrcNumber[3]" = "1" - register "PcieRpClkSrcNumber[4]" = "2" - register "PcieRpClkSrcNumber[8]" = "3" - register "PcieRpClkSrcNumber[9]" = "3" - register "PcieRpClkSrcNumber[10]" = "3" - register "PcieRpClkSrcNumber[11]" = "3"
# PL2 override 25W register "power_limits_config" = "{ @@ -154,19 +140,38 @@ }" register "SataSpeedLimit" = "2" end - device ref pcie_rp3 on end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "1" + end + device ref pcie_rp4 on + register "PcieRpEnable[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "1" + end device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "2" smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" "SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X" end device ref pcie_rp6 on end device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "3" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "SSD_M.2 2242/2280" "SlotDataBusWidth4X" end - device ref pcie_rp10 on end - device ref pcie_rp11 on end - device ref pcie_rp12 on end + device ref pcie_rp10 on + register "PcieRpEnable[9]" = "1" + register "PcieRpClkSrcNumber[9]" = "3" + end + device ref pcie_rp11 on + register "PcieRpEnable[10]" = "1" + register "PcieRpClkSrcNumber[10]" = "3" + end + device ref pcie_rp12 on + register "PcieRpEnable[11]" = "1" + register "PcieRpClkSrcNumber[11]" = "3" + end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS"
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 228676b..3369502 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -98,48 +98,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
- # Enable Root ports. 1-6 for LAN and Root Port 9 - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[8]" = "1" # mPCIe WiFi - - # Enable Advanced Error Reporting for RP 1-6, 9 - register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpAdvancedErrorReporting[1]" = "1" - register "PcieRpAdvancedErrorReporting[2]" = "1" - register "PcieRpAdvancedErrorReporting[3]" = "1" - register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpAdvancedErrorReporting[5]" = "1" - register "PcieRpAdvancedErrorReporting[8]" = "1" - - # Enable Latency Tolerance Reporting Mechanism RP 1-6, 9 - register "PcieRpLtrEnable[0]" = "1" - register "PcieRpLtrEnable[1]" = "1" - register "PcieRpLtrEnable[2]" = "1" - register "PcieRpLtrEnable[3]" = "1" - register "PcieRpLtrEnable[4]" = "1" - register "PcieRpLtrEnable[5]" = "1" - register "PcieRpLtrEnable[8]" = "1" - - # Enable RP 9 CLKREQ# support - register "PcieRpClkReqSupport[8]" = "1" - # RP 9 uses CLKREQ0# - register "PcieRpClkReqNumber[8]" = "0" - - # Clocks 0-5 for RP 1-6 - register "PcieRpClkSrcNumber[0]" = "0" - register "PcieRpClkSrcNumber[1]" = "1" - register "PcieRpClkSrcNumber[2]" = "2" - register "PcieRpClkSrcNumber[3]" = "3" - register "PcieRpClkSrcNumber[4]" = "4" - register "PcieRpClkSrcNumber[5]" = "5" - # RP 9 shares CLKSRC5# with RP 6 - register "PcieRpClkSrcNumber[8]" = "5" - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, @@ -182,14 +140,56 @@ [1] = 1, }" end - device ref pcie_rp1 on end - device ref pcie_rp2 on end - device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp5 on end - device ref pcie_rp6 on end + device ref pcie_rp1 on + # LAN + register "PcieRpEnable[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "0" + end + device ref pcie_rp2 on + # LAN + register "PcieRpEnable[1]" = "1" + register "PcieRpAdvancedErrorReporting[1]" = "1" + register "PcieRpLtrEnable[1]" = "1" + register "PcieRpClkSrcNumber[1]" = "1" + end + device ref pcie_rp3 on + # LAN + register "PcieRpEnable[2]" = "1" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpClkSrcNumber[2]" = "2" + end + device ref pcie_rp4 on + # LAN + register "PcieRpEnable[3]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "3" + end + device ref pcie_rp5 on + # LAN + register "PcieRpEnable[4]" = "1" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "4" + end + device ref pcie_rp6 on + # LAN + register "PcieRpEnable[5]" = "1" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieRpClkSrcNumber[5]" = "5" + end device ref pcie_rp9 on - # WIFI + # mPCIe WIFI + register "PcieRpEnable[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "5" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "0" smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index ca18f7a..01ae0f2 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -123,10 +123,6 @@ .dc_loadline = 420, }"
- # Enable Root Ports 5 and 9 - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - # PL2 override 25W register "power_limits_config" = "{ .tdp_pl2_override = 25, @@ -147,8 +143,12 @@ [2] = 1, }" end - device ref pcie_rp5 on end - device ref pcie_rp9 on end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + end device ref lpc_espi on # EC/KBC requires continuous mode register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb index fa76a78..8a2bf28 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb @@ -1,10 +1,5 @@ chip soc/intel/skylake
- # Disable CLKREQ# for RP9 - register "PcieRpClkReqSupport[8]" = "0" - # SRCCLKREQ2# for NVMe per schematic - register "PcieRpClkReqNumber[8]" = "2" - device domain 0 on device ref south_xhci on register "usb2_ports" = "{ @@ -28,5 +23,9 @@ }" end device ref pcie_rp5 on end + device ref pcie_rp9 on + register "PcieRpClkReqSupport[8]" = "0" + register "PcieRpClkReqNumber[8]" = "2" + end end end diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index b8ebb1b..d386397 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -102,17 +102,6 @@ .dc_loadline = 310, }"
- # Enable Root Ports 3, 5 and 9 - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - - register "PcieRpLtrEnable[2]" = "1" - register "PcieRpLtrEnable[4]" = "1" - register "PcieRpLtrEnable[8]" = "1" - - register "PcieRpHotPlug[4]" = "1" - # PL1 override 25W # PL2 override 44W register "power_limits_config" = "{ @@ -167,8 +156,19 @@ device ref heci1 on end device ref uart2 on end device ref pcie_rp1 on end - device ref pcie_rp5 on end - device ref pcie_rp9 on end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS"
-
Felix Singer (Code Review)