Change in coreboot[master]: mb/google/puff: Implement cse_board_reset() strong symbol

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44454 )

Change subject: mb/google/puff: Implement cse_board_reset() strong symbol
......................................................................

mb/google/puff: Implement cse_board_reset() strong symbol

Since Puff uses CSE Lite SKU that supports in-field CSME
updates an additional reset is triggered when jmp from RO
to RW during boot. However this reset is not detected by
the cr50 running older firmware because the strapping
configuration for EFS2 uses PLT_RST_L to assert to cr50
that a AP reset occured. However, the older cr50 firmware
version of 0.0.22 only monitors AP resets via SYS_RESET_L
and hence never detects the reset.

To mitigate the issue above a modified reset sequence is
required to be performed to signal the reset occured and
hence a board-specific cse_board_reset() strong symbol is
provided to modify the flow accordingly.

N.B, $(CONFIG_BOARD_GOOGLE_BASEBOARD_PUFF) += mainboard.c
     and so Hatch is un-impacted by this.

BUG=b:162290856
BRANCH=puff
TEST=none

Change-Id: I27ab9711aedf92b5af7a58f3b5472ce79f78c8fa
Signed-off-by: Edward O'Callaghan 
---
M src/mainboard/google/hatch/variants/baseboard/mainboard.c
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/44454/1

diff --git a/src/mainboard/google/hatch/variants/baseboard/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c
index 537e3df..0538d22 100644
--- a/src/mainboard/google/hatch/variants/baseboard/mainboard.c
+++ b/src/mainboard/google/hatch/variants/baseboard/mainboard.c
@@ -8,6 +8,8 @@
 #include <device/pci_ops.h>
 #include <ec/google/chromeec/ec.h>
 #include <gpio.h>
+#include <halt.h>
+#include <intelblocks/cse.h>
 #include <intelblocks/power_limit.h>
 #include <soc/pci_devs.h>
 #include <timer.h>
@@ -147,6 +149,13 @@
    conf->tdp_psyspl2 = psyspl2;
 }

+void cse_board_reset(void)
+{
+	/* TODO: Check TPM firmware version before initiating AP reset. */
+	if (!google_chromeec_ap_reset())
+		halt();
+}
+
 void variant_ramstage_init(void)
 {
    static const long display_timeout_ms = 3000;

[Kangheui Won (Code Review)]

Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44454 )

Change subject: mb/google/puff: Implement cse_board_reset() strong symbol
......................................................................

Patch Set 1:

I'm not sure how coreboot/chromium CQ handle chains, but does this need to be rebased on https://review.coreboot.org/c/coreboot/+/44188?

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44454 )

Change subject: mb/google/puff: Implement cse_board_reset() strong symbol
......................................................................

Patch Set 1:
> Patch Set 1:
>
> I'm not sure how coreboot/chromium CQ handle chains, but does this need to be rebased on https://review.coreboot.org/c/coreboot/+/44188?

That's right, we have to wait until authors are happy to merge the required depencies.

[Sam McNally (Code Review)]

Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44454 )

Change subject: mb/google/puff: Implement cse_board_reset() strong symbol
......................................................................

Patch Set 1: Code-Review+2

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44454 )

Change subject: mb/google/puff: Implement cse_board_reset() strong symbol
......................................................................

Patch Set 2: Code-Review+2

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44454 )

Change subject: mb/google/puff: Implement cse_board_reset() strong symbol
......................................................................

Patch Set 2: Code-Review-2

Will squash in https://review.coreboot.org/c/coreboot/+/44278/ here as well once the tpm refactor lands.

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44454 )

Change subject: mb/google/puff: Implement cse_board_reset() strong symbol
......................................................................

Patch Set 2: -Code-Review

Change in coreboot[master]: mb/google/puff: Select cse_board_reset() strong symbol

[Edward O'Callaghan (Code Review)]

Hello Sam McNally, build bot (Jenkins), Furquan Shaikh, Karthik Ramasubramanian, Kangheui Won,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44454

to look at the new patch set (#3).

Change subject: mb/google/puff: Select cse_board_reset() strong symbol
......................................................................

mb/google/puff: Select cse_board_reset() strong symbol

Since Puff uses CSE Lite SKU that supports in-field CSME
updates an additional reset is triggered when jmp from RO
to RW during boot. However this reset is not detected by
the cr50 running older firmware because the strapping
configuration for EFS2 uses PLT_RST_L to assert to cr50
that a AP reset occured. The older cr50 firmware
version of 0.0.22 only monitors AP resets via SYS_RESET_L
and hence never detects the reset.

To mitigate the issue above a modified reset sequence is
required to be performed to signal the reset occured and
hence a board-specific cse_board_reset() strong symbol is
provided to modify the flow accordingly.

V.2: Select CHROMEOS_CSE_BOARD_RESET_OVERRIDE common
     implementation instead of a local variant in mainboard.c

BUG=b:162290856
BRANCH=puff
TEST=none

Change-Id: I27ab9711aedf92b5af7a58f3b5472ce79f78c8fa
Signed-off-by: Edward O'Callaghan 
---
M src/mainboard/google/hatch/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/44454/3

Change in coreboot[master]: mb/google/puff: Select cse_board_reset() strong symbol

[Sam McNally (Code Review)]

Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44454 )

Change subject: mb/google/puff: Select cse_board_reset() strong symbol
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: mb/google/puff: Select cse_board_reset() strong symbol

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44454 )

Change subject: mb/google/puff: Select cse_board_reset() strong symbol
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: mb/google/puff: Select cse_board_reset() strong symbol

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44454 )

Change subject: mb/google/puff: Select cse_board_reset() strong symbol
......................................................................

mb/google/puff: Select cse_board_reset() strong symbol

Since Puff uses CSE Lite SKU that supports in-field CSME
updates an additional reset is triggered when jmp from RO
to RW during boot. However this reset is not detected by
the cr50 running older firmware because the strapping
configuration for EFS2 uses PLT_RST_L to assert to cr50
that a AP reset occured. The older cr50 firmware
version of 0.0.22 only monitors AP resets via SYS_RESET_L
and hence never detects the reset.

To mitigate the issue above a modified reset sequence is
required to be performed to signal the reset occured and
hence a board-specific cse_board_reset() strong symbol is
provided to modify the flow accordingly.

V.2: Select CHROMEOS_CSE_BOARD_RESET_OVERRIDE common
     implementation instead of a local variant in mainboard.c

BUG=b:162290856
BRANCH=puff
TEST=none

Change-Id: I27ab9711aedf92b5af7a58f3b5472ce79f78c8fa
Signed-off-by: Edward O'Callaghan 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44454
Reviewed-by: Sam McNally 
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/hatch/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Sam McNally: Looks good to me, approved

diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index f369949..a658b2a 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -52,6 +52,7 @@
    select HAS_RECOVERY_MRC_CACHE
    select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
    select VBOOT_LID_SWITCH
+	select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if BOARD_GOOGLE_BASEBOARD_PUFF

config CHROMEOS_WIFI_SAR
    bool "Enable SAR options for Chrome OS build"