[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

[Subrata Banik (Code Review)]

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Krishna P Bhat D, Pranava Y N, Saurabh Mishra.

Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
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Patch Set 89:

(4 comments)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83798/comment/b3a8fbc6_a9ae9649?usp... :
PS50, Line 69: SOC_INTEL_COMMON_BLOCK_ME_SPEC_18
> @[e-mail] Please update the 21.0 ME spec.

if you need more time, then please add a TODO and add into the bug to continue

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83798/comment/f4c602ad_8061bd70?usp... :
PS71, Line 367: config FSP_PUBLISH_MBP_HOB
note, those CLs are not merged yet, hence, you need to rebase your code later as well.

File src/soc/intel/pantherlake/acpi.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/f6a5728a_7eb92cc0?usp... :
PS37, Line 30: 	C_STATE_C0,		/* 0 */
             : 	C_STATE_C1,		/* 1 */
             : 	C_STATE_C1E,		/* 2 */
             : 	C_STATE_C6_SHORT_LAT,	/* 3 */
             : 	C_STATE_C6_LONG_LAT,	/* 4 */
             : 	C_STATE_C7_SHORT_LAT,	/* 5 */
             : 	C_STATE_C7_LONG_LAT,	/* 6 */
             : 	C_STATE_C7S_SHORT_LAT,	/* 7 */
             : 	C_STATE_C7S_LONG_LAT,	/* 8 */
             : 	C_STATE_C8,		/* 9 */
             : 	C_STATE_C9,		/* 10 */
             : 	C_STATE_C10,		/* 11 */
             : 	NUM_C_STATES
> Hi, I will be back on this info. Checking internally with the owners.

can you please move this also as TODO task and add an entry into the bug. Then please close this comment?

File src/soc/intel/pantherlake/include/soc/cpu.h:

https://review.coreboot.org/c/coreboot/+/83798/comment/fa55c170_d44bf247?usp... :
PS71, Line 15: #define C1_POWER	0x3e8
             : #define C6_POWER	0x15e
             : #define C7_POWER	0xc8
             : #define C8_POWER	0xc8
             : #define C9_POWER	0xc8
             : #define C10_POWER	0xc8
> please confirm the applicability and authenticity of these values  for PTL SoC.

please also move this into the bug as TODO and then resolve this comment