Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43130 )
Change subject: nb/intel/haswell/romstage.c: Align pei_data initializers ......................................................................
nb/intel/haswell/romstage.c: Align pei_data initializers
Aligned initializers should be easier to read.
Change-Id: If9238177c4959d80444fc842fd83794bfdac5c4b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/romstage.c 1 file changed, 19 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/43130/1
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index fdab8eb..a1103c4 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -46,25 +46,25 @@ int wake_from_s3;
struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = get_pch_platform_type(), - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .ec_present = cfg->ec_present, - .gbe_enable = gbe && gbe->enabled, - .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), - .dq_pins_interleaved = cfg->dq_pins_interleaved, - .max_ddr3_freq = 1600, - .usb_xhci_on_resume = cfg->usb_xhci_on_resume, + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = get_pch_platform_type(), + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .ec_present = cfg->ec_present, + .gbe_enable = gbe && gbe->enabled, + .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), + .dq_pins_interleaved = cfg->dq_pins_interleaved, + .max_ddr3_freq = 1600, + .usb_xhci_on_resume = cfg->usb_xhci_on_resume, };
mainboard_fill_pei_data(&pei_data);
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43130
to look at the new patch set (#2).
Change subject: nb/intel/haswell/romstage.c: Align pei_data initializers ......................................................................
nb/intel/haswell/romstage.c: Align pei_data initializers
Aligned initializers should be easier to read.
Change-Id: If9238177c4959d80444fc842fd83794bfdac5c4b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/romstage.c 1 file changed, 19 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/43130/2
Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43130 )
Change subject: nb/intel/haswell/romstage.c: Align pei_data initializers ......................................................................
Patch Set 2: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43130 )
Change subject: nb/intel/haswell/romstage.c: Align pei_data initializers ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43130 )
Change subject: nb/intel/haswell/romstage.c: Align pei_data initializers ......................................................................
nb/intel/haswell/romstage.c: Align pei_data initializers
Aligned initializers should be easier to read.
Change-Id: If9238177c4959d80444fc842fd83794bfdac5c4b Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43130 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tristan Corrick tristan@corrick.kiwi Reviewed-by: Michael Niewöhner --- M src/northbridge/intel/haswell/romstage.c 1 file changed, 19 insertions(+), 19 deletions(-)
Approvals: build bot (Jenkins): Verified Tristan Corrick: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index dfadad2..39babf5 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -46,25 +46,25 @@ int wake_from_s3;
struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = get_pch_platform_type(), - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .ec_present = cfg->ec_present, - .gbe_enable = gbe && gbe->enabled, - .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), - .dq_pins_interleaved = cfg->dq_pins_interleaved, - .max_ddr3_freq = 1600, - .usb_xhci_on_resume = cfg->usb_xhci_on_resume, + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = get_pch_platform_type(), + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .ec_present = cfg->ec_present, + .gbe_enable = gbe && gbe->enabled, + .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), + .dq_pins_interleaved = cfg->dq_pins_interleaved, + .max_ddr3_freq = 1600, + .usb_xhci_on_resume = cfg->usb_xhci_on_resume, };
mainboard_fill_pei_data(&pei_data);
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)
-
Tristan Corrick (Code Review)