Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69705 )
Change subject: mb/amd/birman: Update DXIO descriptors per schematic ......................................................................
mb/amd/birman: Update DXIO descriptors per schematic
Update DXIO descriptors for birman-phoenix per schematic 105-D67000-00B v0.7
Update devicetree to reference the updated DXIO descriptors.
TEST=boot birman and note the devices show up in the logs correctly
Signed-off-by: Fred Reitberger reitbergerfred@gmail.com Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/69705 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/birman/port_descriptors_phoenix.c 2 files changed, 199 insertions(+), 52 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index 9cebaab..ff54e1f 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -151,16 +151,23 @@ .PhyP3CpmP4Support = 0, }"
- register "gpp_clk_config[0]" = "GPP_CLK_REQ" - register "gpp_clk_config[1]" = "GPP_CLK_REQ" - register "gpp_clk_config[2]" = "GPP_CLK_OFF" - register "gpp_clk_config[3]" = "GPP_CLK_REQ" + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # MXM + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # NVMe SSD1 + register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVMe SSD0 + register "gpp_clk_config[3]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[4]" = "GPP_CLK_REQ" # WWAN + register "gpp_clk_config[5]" = "GPP_CLK_REQ" # SD + register "gpp_clk_config[6]" = "GPP_CLK_REQ" # GBE
device domain 0 on device ref iommu on end - device ref gpp_bridge_2_1 on end # GBE - device ref gpp_bridge_2_2 on end # WIFI - device ref gpp_bridge_2_3 on end # NVMe SSD + device ref gpp_bridge_1_1 on end # MXM + device ref gpp_bridge_1_2 on end # NVMe SSD1 + device ref gpp_bridge_1_3 on end # GBE + device ref gpp_bridge_2_1 on end # SD + device ref gpp_bridge_2_2 on end # WWAN + device ref gpp_bridge_2_3 on end # WIFI + device ref gpp_bridge_2_4 on end # NVMe SSD0 device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/mainboard/amd/birman/port_descriptors_phoenix.c b/src/mainboard/amd/birman/port_descriptors_phoenix.c index df961bf..d254eea 100644 --- a/src/mainboard/amd/birman/port_descriptors_phoenix.c +++ b/src/mainboard/amd/birman/port_descriptors_phoenix.c @@ -4,52 +4,136 @@ #include <device/i2c_simple.h> #include <gpio.h> #include <soc/platform_descriptors.h> +#include <soc/soc_util.h> #include <types.h>
-/* TODO: Update for birman */ +#define phx_mxm_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = CONFIG(ENABLE_EVAL_CARD), \ + .start_logical_lane = 0, \ + .end_logical_lane = 7, \ + .device_number = 1, \ + .function_number = 1, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ0, \ +}
-static const fsp_dxio_descriptor birman_dxio_descriptors[] = { - { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = 2, - .function_number = 1, - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = 3, - .clk_req = CLK_REQ3, - }, - { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 1, - .end_logical_lane = 1, - .device_number = 2, - .function_number = 2, - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = 3, - .clk_req = CLK_REQ1, - }, - { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 2, - .end_logical_lane = 3, - .device_number = 2, - .function_number = 3, - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = 3, - .gpio_group_id = GPIO_27, - .clk_req = CLK_REQ0, - }, -}; +/* TODO: verify on hardware */ +#define phx2_mxm_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = CONFIG(ENABLE_EVAL_CARD), \ + .start_logical_lane = 0, \ + .end_logical_lane = 3, \ + .device_number = 1, \ + .function_number = 1, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ0, \ +} + +#define phx_ssd1_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = !CONFIG(DISABLE_DT_M2), \ + .start_logical_lane = 8, \ + .end_logical_lane = 11, \ + .device_number = 1, \ + .function_number = 2, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ1, \ +} + +/* TODO: verify on hardware */ +#define phx2_ssd1_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 8, \ + .end_logical_lane = 9, \ + .device_number = 1, \ + .function_number = 2, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ1, \ +} + +#define gbe_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 12, \ + .end_logical_lane = 12, \ + .device_number = 1, \ + .function_number = 3, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ6, \ +} + +#define sd_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 13, \ + .end_logical_lane = 13, \ + .device_number = 2, \ + .function_number = 1, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ5, \ +} + +#define wwan_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 14, \ + .end_logical_lane = CONFIG(WWAN01) ? 15 : 14, \ + .device_number = 2, \ + .function_number = 2, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ4, \ +} + +#define wlan_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 15, \ + .end_logical_lane = CONFIG(WLAN01) ? 14 : 15, \ + .device_number = 2, \ + .function_number = 3, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ3, \ +} + +#define ssd0_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 16, \ + .end_logical_lane = 19, \ + .device_number = 2, \ + .function_number = 4, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ2, \ +}
static fsp_ddi_descriptor birman_ddi_descriptors[] = { { /* DDI0 - eDP */ @@ -123,8 +207,44 @@ { birman_ddi_descriptors[1].connector_type = get_ddi1_type();
- *dxio_descs = birman_dxio_descriptors; - *dxio_num = ARRAY_SIZE(birman_dxio_descriptors); + enum soc_type type = get_soc_type(); + + if (type == SOC_PHOENIX) { + printk(BIOS_DEBUG, "Using PHX DXIO\n"); + static const fsp_dxio_descriptor birman_phx_dxio_descriptors[] = { + phx_mxm_dxio_descriptor, + phx_ssd1_dxio_descriptor, + gbe_dxio_descriptor, + sd_dxio_descriptor, +#if CONFIG(WLAN0_WWAN0) || CONFIG(WWAN01) + wwan_dxio_descriptor, +#endif +#if CONFIG(WLAN0_WWAN0) || CONFIG(WLAN01) + wlan_dxio_descriptor, +#endif + ssd0_dxio_descriptor, + }; + *dxio_descs = birman_phx_dxio_descriptors; + *dxio_num = ARRAY_SIZE(birman_phx_dxio_descriptors); + } else { + printk(BIOS_DEBUG, "Using PHX2 DXIO\n"); + static const fsp_dxio_descriptor birman_phx2_dxio_descriptors[] = { + phx2_mxm_dxio_descriptor, + phx2_ssd1_dxio_descriptor, + gbe_dxio_descriptor, + sd_dxio_descriptor, +#if CONFIG(WLAN0_WWAN0) || CONFIG(WWAN01) + wwan_dxio_descriptor, +#endif +#if CONFIG(WLAN0_WWAN0) || CONFIG(WLAN01) + wlan_dxio_descriptor, +#endif + ssd0_dxio_descriptor, + }; + *dxio_descs = birman_phx2_dxio_descriptors; + *dxio_num = ARRAY_SIZE(birman_phx2_dxio_descriptors); + } + *ddi_descs = birman_ddi_descriptors; *ddi_num = ARRAY_SIZE(birman_ddi_descriptors); }
-
Felix Held (Code Review)