Change in coreboot[master]: mb/google/zork: Move PCIE_RST0_L configuration to early GPIO table

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42739 )

Change subject: mb/google/zork: Move PCIE_RST0_L configuration to early GPIO table
......................................................................

mb/google/zork: Move PCIE_RST0_L configuration to early GPIO table

This change moves the configuration of PCIE_RST0_L as native
function to happen in early GPIO table. This ensures that the PERST#
signal is deasserted as soon as possible when the system comes out
of sleep state in case the sleep path asserted/deasserted the PERST#
as GPIO out.

A big difference in functionality with this change is that PCIE_RST0_L
signal is now configured as part of RO, which should be fine since
all PCIe devices have a second AUX_RESET_L signal or use PCIE_RST1_L
to control the actual reset to the device.

Signed-off-by: Furquan Shaikh 
Change-Id: I21a9c25b5a8a6d502cdb79cbe0dbad6ef98d6d63
---
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
3 files changed, 2 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/42739/1

diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
index e903700..a4e8648 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
@@ -13,6 +13,8 @@
    PAD_NF(GPIO_19, I2C3_SCL, PULL_UP),
    /* I2C3_SDA - H1 */
    PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),
+	/* PCIE_RST0_L - Fixed timings */
+	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
    /* FCH_ESPI_EC_CS_L */
    PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
    /* ESPI_ALERT_L (may be unused) */
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index d4ed86e..d6343a6 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -15,9 +15,6 @@
    /* EC_FCH_WAKE_L */
    PAD_GPI(GPIO_24, PULL_UP),
    PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
-	/* PCIE_RST0_L - Fixed timings */
-	/* TODO: Make sure this gets locked at end of post */
-	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
    /* PCIE_RST1_L - Variable timings (May remove) */
    PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
    /* NVME_AUX_RESET_L */
@@ -52,9 +49,6 @@
    /* EC_FCH_WAKE_L */
    PAD_GPI(GPIO_24, PULL_UP),
    PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
-	/* PCIE_RST0_L - Fixed timings */
-	/* TODO: Make sure this gets locked at end of post */
-	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
    /* PCIE_RST1_L - Variable timings (May remove) */
    PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
    /* NVME_AUX_RESET_L */
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index abee520..f93309d 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -15,9 +15,6 @@
    /* EC_FCH_WAKE_L */
    PAD_GPI(GPIO_24, PULL_UP),
    PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
-	/* PCIE_RST0_L - Fixed timings */
-	/* TODO: Make sure this gets locked at end of post */
-	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
    /* PCIE_RST1_L - Variable timings (May remove) */
    PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
    /* NVME_AUX_RESET_L */
@@ -50,9 +47,6 @@
    /* EC_FCH_WAKE_L */
    PAD_GPI(GPIO_24, PULL_UP),
    PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
-	/* PCIE_RST0_L - Fixed timings */
-	/* TODO: Make sure this gets locked at end of post */
-	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
    /* PCIE_RST1_L - Variable timings (May remove) */
    PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
    /* NVME_AUX_RESET_L */

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42739 )

Change subject: mb/google/zork: Move PCIE_RST0_L configuration to early GPIO table
......................................................................

Patch Set 2: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42739 )

Change subject: mb/google/zork: Move PCIE_RST0_L configuration to early GPIO table
......................................................................

mb/google/zork: Move PCIE_RST0_L configuration to early GPIO table

This change moves the configuration of PCIE_RST0_L as native
function to happen in early GPIO table. This ensures that the PERST#
signal is deasserted as soon as possible when the system comes out
of sleep state in case the sleep path asserted/deasserted the PERST#
as GPIO out.

A big difference in functionality with this change is that PCIE_RST0_L
signal is now configured as part of RO, which should be fine since
all PCIe devices have a second AUX_RESET_L signal or use PCIE_RST1_L
to control the actual reset to the device.

Signed-off-by: Furquan Shaikh 
Change-Id: I21a9c25b5a8a6d502cdb79cbe0dbad6ef98d6d63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42739
Reviewed-by: Aaron Durbin 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
3 files changed, 2 insertions(+), 12 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved

diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
index e903700..a4e8648 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
@@ -13,6 +13,8 @@
    PAD_NF(GPIO_19, I2C3_SCL, PULL_UP),
    /* I2C3_SDA - H1 */
    PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),
+	/* PCIE_RST0_L - Fixed timings */
+	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
    /* FCH_ESPI_EC_CS_L */
    PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
    /* ESPI_ALERT_L (may be unused) */
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index 35e1829..ba50362 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -15,9 +15,6 @@
    /* EC_FCH_WAKE_L */
    PAD_GPI(GPIO_24, PULL_UP),
    PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
-	/* PCIE_RST0_L - Fixed timings */
-	/* TODO: Make sure this gets locked at end of post */
-	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
    /* PCIE_RST1_L - Variable timings (May remove) */
    PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
    /* NVME_AUX_RESET_L */
@@ -52,9 +49,6 @@
    /* EC_FCH_WAKE_L */
    PAD_GPI(GPIO_24, PULL_UP),
    PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
-	/* PCIE_RST0_L - Fixed timings */
-	/* TODO: Make sure this gets locked at end of post */
-	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
    /* PCIE_RST1_L - Variable timings (May remove) */
    PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
    /* NVME_AUX_RESET_L */
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index 3f02f00..01aef2b 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -15,9 +15,6 @@
    /* EC_FCH_WAKE_L */
    PAD_GPI(GPIO_24, PULL_UP),
    PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
-	/* PCIE_RST0_L - Fixed timings */
-	/* TODO: Make sure this gets locked at end of post */
-	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
    /* PCIE_RST1_L - Variable timings (May remove) */
    PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
    /* NVME_AUX_RESET_L */
@@ -50,9 +47,6 @@
    /* EC_FCH_WAKE_L */
    PAD_GPI(GPIO_24, PULL_UP),
    PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
-	/* PCIE_RST0_L - Fixed timings */
-	/* TODO: Make sure this gets locked at end of post */
-	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
    /* PCIE_RST1_L - Variable timings (May remove) */
    PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
    /* NVME_AUX_RESET_L */