Change in coreboot[master]: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl file
Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35028 )
Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl file ......................................................................
superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl file
This port is based on NCT6776
Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 --- A src/superio/nuvoton/nct5539d/acpi/superio.asl 1 file changed, 171 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35028/1
diff --git a/src/superio/nuvoton/nct5539d/acpi/superio.asl b/src/superio/nuvoton/nct5539d/acpi/superio.asl new file mode 100644 index 0000000..45ce018 --- /dev/null +++ b/src/superio/nuvoton/nct5539d/acpi/superio.asl @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz christophg+cb@grenz-bonn.de + * Copyright (C) 2013, 2016 secunet Security Networks AG + * Copyright (C) 2017 Tobias Diedrich ranma+coreboot@tdiedrich.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the NCT5539D SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x2 SP1 Implemented, untested + * 0x5 KBC Implemented, untested + * 0x8 GPIO Implemented, untested + * 0xb HWM Implemented, untested + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * NCT5539D_SHOW_SP1 If defined, Serial Port 1 will be exposed. + * NCT5539D_SHOW_KBC If defined, the Keyboard Controller will be exposed. + * NCT5539D_SHOW_GPIO If defined, GPIO support will be exposed. + * NCT5539D_SHOW_HWM If defined, the Environment Controller will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME NCT5539D +#include <superio/acpi/pnp.asl> + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Nuvoton NCT5539D Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8, + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + ACT1, 1, /* Logical device activation */ + ACT2, 1, /* Logical device activation */ + ACT3, 1, /* Logical device activation */ + ACT4, 1, /* Logical device activation */ + ACT5, 1, /* Logical device activation */ + ACT6, 1, /* Logical device activation */ + ACT7, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x64), + PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ + PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + Offset (0x72), + PNP_IRQ1, 8, /* Second IRQ */ + Offset (0x74), + PNP_DMA0, 8, /* DRQ */ + } + + Method (_CRS) + { + /* Announce the used I/O ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + + +#ifdef NCT5539D_SHOW_SP1 + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef NCT5539D_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 + #define SUPERIO_KBC_PS2M + #include <superio/acpi/pnp_kbc.asl> +#endif + +#ifdef NCT5539D_SHOW_HWM + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_LDN 11 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IO1 0x08, 0x08 + #define SUPERIO_PNP_IRQ0 + #include <superio/acpi/pnp_generic.asl> +#endif + +#ifdef NCT5539D_SHOW_GPIO + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #undef PNP_DEVICE_ACTIVE + #define PNP_DEVICE_ACTIVE ACT3 + #define SUPERIO_PNP_LDN 8 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #include <superio/acpi/pnp_generic.asl> +#endif +}
Hello Felix Held, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35028
to look at the new patch set (#2).
Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl ......................................................................
superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl
This port is based on NCT6776
Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/superio/nuvoton/nct5539d/acpi/superio.asl 1 file changed, 172 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35028/2
Hello Felix Held, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35028
to look at the new patch set (#3).
Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl ......................................................................
superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl
This port is based on NCT6776
Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/superio/nuvoton/nct5539d/acpi/superio.asl 1 file changed, 172 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35028/3
Hello Felix Held, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35028
to look at the new patch set (#5).
Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl ......................................................................
superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl
This port is based on NCT6776
Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/superio/nuvoton/nct5539d/acpi/superio.asl 1 file changed, 172 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35028/5
Hello Felix Held, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35028
to look at the new patch set (#6).
Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl ......................................................................
superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl
This port is based on NCT6776
Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/superio/nuvoton/nct5539d/acpi/superio.asl 1 file changed, 172 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35028/6
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35028 )
Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35028/7/src/superio/nuvoton/nct5539... File src/superio/nuvoton/nct5539d/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/35028/7/src/superio/nuvoton/nct5539... PS7, Line 167: #define PNP_DEVICE_ACTIVE ACT3 this is for one specific GPIO bank, right? is this intended?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35028 )
Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35028/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35028/7//COMMIT_MSG@10 PS7, Line 10: Please describe, what works now, and how you tested this.
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35028 )
Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl ......................................................................
Patch Set 7:
(2 comments)
o/
https://review.coreboot.org/c/coreboot/+/35028/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35028/7//COMMIT_MSG@10 PS7, Line 10:
Please describe, what works now, and how you tested this.
It is sourced from NCT6776 as it is directly used for NCT6791D for asrock-h110m-dvs port but just to make it independent from NCT6776 so that if any modifications needed can be done without touching NCT6776/acpi/superio.asl file and it is getting tested along with the https://review.coreboot.org/c/coreboot/+/34603 as a whole (or as a pair you can say).
https://review.coreboot.org/c/coreboot/+/35028/7/src/superio/nuvoton/nct5539... File src/superio/nuvoton/nct5539d/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/35028/7/src/superio/nuvoton/nct5539... PS7, Line 167: #define PNP_DEVICE_ACTIVE ACT3
this is for one specific GPIO bank, right? is this intended?
That is just copied form superio/nuvoton/nct6776/acpi/superio.asl with a view that if any NCT5539D specific mod needed that could be done independently. Don't have very clear idea about it, perhaps you can tell me.
Hello Felix Held, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35028
to look at the new patch set (#9).
Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl ......................................................................
superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl
This port is based on NCT6776
Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/superio/nuvoton/nct5539d/acpi/superio.asl 1 file changed, 172 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35028/9
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35028 )
Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl ......................................................................
Patch Set 9:
(1 comment)
o/
https://review.coreboot.org/c/coreboot/+/35028/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35028/7//COMMIT_MSG@10 PS7, Line 10:
It is sourced from NCT6776 as it is directly used for NCT6791D for asrock-h110m-dvs port but just to […]
So far the serial output of coreboot which leads to a blank display with a blinking cursor, https://pastebin.com/S9tLjhwb
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35028 )
Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl ......................................................................
Patch Set 9: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/35028/7/src/superio/nuvoton/nct5539... File src/superio/nuvoton/nct5539d/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/35028/7/src/superio/nuvoton/nct5539... PS7, Line 167: #define PNP_DEVICE_ACTIVE ACT3
That is just copied form superio/nuvoton/nct6776/acpi/superio. […]
ah, had a look again and this is for the gpio interface in the i/o space
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35028 )
Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35028/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35028/7//COMMIT_MSG@10 PS7, Line 10:
So far the serial output of coreboot which leads to a blank display with a blinking cursor, https:// […]
Done
https://review.coreboot.org/c/coreboot/+/35028/7/src/superio/nuvoton/nct5539... File src/superio/nuvoton/nct5539d/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/35028/7/src/superio/nuvoton/nct5539... PS7, Line 167: #define PNP_DEVICE_ACTIVE ACT3
ah, had a look again and this is for the gpio interface in the i/o space
Done
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35028 )
Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl ......................................................................
superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl
This port is based on NCT6776
Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35028 Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/superio/nuvoton/nct5539d/acpi/superio.asl 1 file changed, 172 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/superio/nuvoton/nct5539d/acpi/superio.asl b/src/superio/nuvoton/nct5539d/acpi/superio.asl new file mode 100644 index 0000000..e259b01 --- /dev/null +++ b/src/superio/nuvoton/nct5539d/acpi/superio.asl @@ -0,0 +1,172 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz christophg+cb@grenz-bonn.de + * Copyright (C) 2013, 2016 secunet Security Networks AG + * Copyright (C) 2017 Tobias Diedrich ranma+coreboot@tdiedrich.de + * Copyright (C) 2019 Pavel Sayekat pavelsayekat@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the NCT5539D SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x2 SP1 Implemented, untested + * 0x5 KBC Implemented, untested + * 0x8 GPIO Implemented, untested + * 0xb HWM Implemented, untested + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * NCT5539D_SHOW_SP1 If defined, Serial Port 1 will be exposed. + * NCT5539D_SHOW_KBC If defined, the Keyboard Controller will be exposed. + * NCT5539D_SHOW_GPIO If defined, GPIO support will be exposed. + * NCT5539D_SHOW_HWM If defined, the Environment Controller will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME NCT5539D +#include <superio/acpi/pnp.asl> + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Nuvoton NCT5539D Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8, + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + ACT1, 1, /* Logical device activation */ + ACT2, 1, /* Logical device activation */ + ACT3, 1, /* Logical device activation */ + ACT4, 1, /* Logical device activation */ + ACT5, 1, /* Logical device activation */ + ACT6, 1, /* Logical device activation */ + ACT7, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x64), + PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ + PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + Offset (0x72), + PNP_IRQ1, 8, /* Second IRQ */ + Offset (0x74), + PNP_DMA0, 8, /* DRQ */ + } + + Method (_CRS) + { + /* Announce the used I/O ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + + +#ifdef NCT5539D_SHOW_SP1 + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef NCT5539D_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 + #define SUPERIO_KBC_PS2M + #include <superio/acpi/pnp_kbc.asl> +#endif + +#ifdef NCT5539D_SHOW_HWM + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_LDN 11 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IO1 0x08, 0x08 + #define SUPERIO_PNP_IRQ0 + #include <superio/acpi/pnp_generic.asl> +#endif + +#ifdef NCT5539D_SHOW_GPIO + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #undef PNP_DEVICE_ACTIVE + #define PNP_DEVICE_ACTIVE ACT3 + #define SUPERIO_PNP_LDN 8 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #include <superio/acpi/pnp_generic.asl> +#endif +}
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