[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines

[Cliff Huang (Code Review)]

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )

Change subject: soc/intel/ptl: Add GPE1 defines
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Patch Set 6:

(1 comment)

File src/soc/intel/pantherlake/include/soc/gpe.h:

https://review.coreboot.org/c/coreboot/+/84297/comment/771f3f7d_c1040356?usp... :
PS4, Line 30: 146
> with block number: […]

18 is the bit 18 defined in GPE1_STS_31_0 (0x10) and GPE1_EN_31_0 (0x1C) registers.

0x80 is GPE0_REG_MAX x sizeof(uint32_t) x 8