Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21672
Change subject: [WIP] asus/p2b-ls: Add ACPI tables ......................................................................
[WIP] asus/p2b-ls: Add ACPI tables
Add ACPI tables support that will be needed for soft-off and S3 resume. Right now only have DSDT and what was done for asus/p2b.
This has not yet been boot tested and so is not for merging yet.
All feedbacks appreciated.
Change-Id: I28b559406bd53efc555dcbb8282dfe2bd6d1af87 Signed-off-by: Keith Hui buurin@gmail.com --- M src/mainboard/asus/p2b-ls/Kconfig A src/mainboard/asus/p2b-ls/acpi_tables.c A src/mainboard/asus/p2b-ls/dsdt.asl 3 files changed, 208 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21672/1
diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig index 967ebd9..2bb9369 100644 --- a/src/mainboard/asus/p2b-ls/Kconfig +++ b/src/mainboard/asus/p2b-ls/Kconfig @@ -23,6 +23,7 @@ select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM + select HAVE_ACPI_TABLES
config MAINBOARD_DIR string diff --git a/src/mainboard/asus/p2b-ls/acpi_tables.c b/src/mainboard/asus/p2b-ls/acpi_tables.c new file mode 100644 index 0000000..d740ee1 --- /dev/null +++ b/src/mainboard/asus/p2b-ls/acpi_tables.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Tobias Diedrich ranma+coreboot@tdiedrich.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* mainboard has no ioapic */ + return current; +} diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl new file mode 100644 index 0000000..7f0d40b --- /dev/null +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -0,0 +1,185 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Keith Hui buurin@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * Mapping of factory BIOS and coreboot ACPI names + * Factory coreboot + * DBG1 P80 + * + * PX40 LPCB + * PIRx PRTx (x=A|B|C|D) + * PIRQ PCIC + * SYSR MBRS (Hardcoded in acpi_tables.c) + * + * PS2K KBD + * PS2M MOU + * ENFG ENCM (ENTER_CONFIG_MODE) + * EXFG EXCM (EXIT_CONFIG_MODE) + * NIDX ADDR + * NDAT DATA + * LDNM LDN (PNP_LOGICAL_DEVICE) + * + */ +#define SUPERIO_PNP_BASE 0x3F0 +#define SUPERIO_DEV W977 +#define WINBOND_SHOW_UARTA +#define WINBOND_SHOW_UARTB +#define WINBOND_SHOW_FDC +#define WINBOND_SHOW_LPT + +DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) +{ + OperationRegion(X80, SystemIO, 0x80, 1) + Field(X80, ByteAcc, NoLock, Preserve) + { + P80, 8 + } + /* Define the main processor. */ + Scope (_PR) + { + /* Looks like the P_CNT field can't be a method or name + * and has to be hardcoded to 0xe410 or generated in SSDT */ + Processor (CPU0, 0x01, 0xe410, 0x06) {} + } + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + + /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */ + /* + 000b / 0x0: soft off/suspend to disk (soff/std) s5 + 001b / 0x1: suspend to ram (str) s3 + 010b / 0x2: powered on suspend, context lost (poscl) s1 + 011b / 0x3: powered on suspend, cpu context lost (posccl) s2 + 100b / 0x4: powered on suspend, context maintained (pos) s4 + 101b / 0x5: working (clock control) s0 + 110b / 0x6: reserved + 111b / 0x7: reserved + */ + Name (_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) + /*Name (_S1, Package () { 0x04, 0x07, 0x00, 0x00 })*/ + Name (_S5, Package () { 0x00, 0x06, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0, LNKA, 0 }, + Package (0x04) { 0x0001FFFF, 1, LNKB, 0 }, + Package (0x04) { 0x0001FFFF, 2, LNKC, 0 }, + Package (0x04) { 0x0001FFFF, 3, LNKD, 0 }, + + Package (0x04) { 0x0004FFFF, 0, LNKA, 0 }, + Package (0x04) { 0x0004FFFF, 1, LNKB, 0 }, + Package (0x04) { 0x0004FFFF, 2, LNKC, 0 }, + Package (0x04) { 0x0004FFFF, 3, LNKD, 0 }, + + Package (0x04) { 0x0006FFFF, 0, LNKD, 0 }, + Package (0x04) { 0x0006FFFF, 1, LNKA, 0 }, + Package (0x04) { 0x0006FFFF, 2, LNKB, 0 }, + Package (0x04) { 0x0006FFFF, 3, LNKC, 0 }, + + Package (0x04) { 0x0009FFFF, 0, LNKD, 0 }, + Package (0x04) { 0x0009FFFF, 1, LNKA, 0 }, + Package (0x04) { 0x0009FFFF, 2, LNKB, 0 }, + Package (0x04) { 0x0009FFFF, 3, LNKC, 0 }, + + Package (0x04) { 0x000AFFFF, 0, LNKC, 0 }, + Package (0x04) { 0x000AFFFF, 1, LNKD, 0 }, + Package (0x04) { 0x000AFFFF, 2, LNKA, 0 }, + Package (0x04) { 0x000AFFFF, 3, LNKB, 0 }, + + Package (0x04) { 0x0007FFFF, 0, LNKC, 0 }, + Package (0x04) { 0x0007FFFF, 1, LNKD, 0 }, + Package (0x04) { 0x0007FFFF, 2, LNKA, 0 }, + Package (0x04) { 0x0007FFFF, 3, LNKB, 0 }, + + Package (0x04) { 0x000BFFFF, 0, LNKB, 0 }, + Package (0x04) { 0x000BFFFF, 1, LNKC, 0 }, + Package (0x04) { 0x000BFFFF, 2, LNKD, 0 }, + Package (0x04) { 0x000BFFFF, 3, LNKA, 0 }, + + Package (0x04) { 0x000CFFFF, 0, LNKA, 0 }, + Package (0x04) { 0x000CFFFF, 1, LNKB, 0 }, + Package (0x04) { 0x000CFFFF, 2, LNKC, 0 }, + Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, + + }) + /* Begin PX40 southbridge block */ +#include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl" +#include "southbridge/intel/i82371eb/acpi/i82371eb.asl" +#include "southbridge/intel/i82371eb/acpi/pirq.asl" + } + } + OperationRegion (GPOB, SystemIO, 0xE42C, 0x10) + Field (GPOB, ByteAcc, NoLock, Preserve) + { + Offset (0x03), + TO12, 1, /* Device trap 12 */ + Offset (0x08), + FANM, 1, /* GPO0, meant for fan */ + Offset (0x09), + PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet this goes low when power is cut from its core. */ + , 3, + , 2, + , 16, + MSG0, 1 /* GPO30, message LED */ + } + + Method (_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep, Arg0 is target S-state + { + If (LNotEqual (Arg0, 0x05)) /* Off */ + { + Store (0x00, FANM) /* \FANM */ + Store (0x00, PLED) /* \PLED */ + } + + If (LEqual (Arg0, 0x01)) + { + Store (One, TO12) /* \TO12, arms SMI for device 12 */ + } + + Store (One, TO12) /* \TO12 */ + Or (Arg0, 0xF0, Local2) + Store (Local2, P80) /* Put out a POST code. */ + } + + /* ACPI Message */ + Scope (_SI) + { + Method (_MSG, 1, NotSerialized) + { + If (LEqual (Arg0, Zero)) + { + Store (One, MSG0) + } + Else + { + Store (Zero, MSG0) + } + } + } +}
-
Keith Hui (Code Review)