Attention is currently required from: Patrick Rudolph, Christian Walter. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58326 )
Change subject: mb/prodrive/hermes: Enable LTR for all PCIe ports ......................................................................
mb/prodrive/hermes: Enable LTR for all PCIe ports
Set the `PcieRpLtrEnable` option to enable LTR on all PCH PCIe ports.
Change-Id: I07ea37d178ea61d904c4f131fdea31479e899ef3 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/58326/1
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 16ba724..9996abd 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -170,30 +170,38 @@ end device pci 1c.4 on # PCIe root port 5 (PHY 3) register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" end device pci 1c.5 on # PCIe root port 6 (PHY 4) register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" end device pci 1c.6 on # PCIe root port 7 (PHY 2) register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" end device pci 1c.7 on # PCIe root port 8 (PHY 1) register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" end device pci 1d.0 on # PCIe root port 9 (M2 M) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" register "PcieRpSlotImplemented[8]" = "1" end device pci 1d.5 on # PCIe root port 14 (PHY 0) register "PcieRpEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "1" end device pci 1d.6 on # PCIe root port 15 (BMC) register "PcieRpEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "1" end device pci 1d.7 on # PCIe root port 16 (M.2 E/CNVi) # Disabled when CNVi is present register "PcieRpEnable[15]" = "1" + register "PcieRpLtrEnable[15]" = "1" register "PcieRpSlotImplemented[15]" = "1" end device pci 1e.0 on end # UART #0