Change in coreboot[master]: soc/intel/common/../cse: Perform D0I3 bit reset/set prior sending EOP

[Angel Pons (Code Review)]

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57805 )

Change subject: soc/intel/common/../cse: Perform D0I3 bit reset/set prior sending EOP
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Patch Set 3:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/57805/comment/cae73dd4_e9d62ab5 
PS3, Line 10: Incase CSE is in Dev Idle state
            : meaning D0I3 bit is set then ensures resetting this bit, prior to
            : sending
            : EOP command.
There's several minor things about this sentence. I'd rephrase it as follows:

In case CSE is in Dev Idle state (which means D0I3 bit is set), reset this bit before sending EOP command.

https://review.coreboot.org/c/coreboot/+/57805/comment/98b7d91d_a3e99666 
PS3, Line 16: evitable
nit: `avoidable` is more common