Change in coreboot[master]: sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36809 )
Change subject: sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x ......................................................................
sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x
The northbridge code to set up DMI is not correct and the CIR bits relate to that.
This fixes a regression caused by 2437fe9 'sb/intel/i82801gx: Move CIR init to a common place', where payloads hang on southbridige IO.
Change-Id: Iabb54d9954d442a1a7b48a6c6e76faa8079a4c71 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/i82801gx/early_init.c 1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/36809/1
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 0bd6198..f91a5dc 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -112,6 +112,9 @@ RCBA8(OIC) = 0x03; RCBA8(OIC);
- ich7_setup_cir(); + /* A lot of CIR bits relate DMI setup which is likely not correctly + done for x4x. The issue is also present on ICH10. */ + if (!CONFIG(NORTHBRIDGE_INTEL_X4X)) + ich7_setup_cir(); } #endif
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36809 )
Change subject: sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/36809/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36809/1//COMMIT_MSG@13 PS1, Line 13: southbridige nit: southbridge
Hello Patrick Rudolph, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36809
to look at the new patch set (#2).
Change subject: sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x ......................................................................
sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x
The northbridge code to set up DMI is not correct and the CIR bits relate to that.
This fixes a regression caused by 2437fe9 'sb/intel/i82801gx: Move CIR init to a common place', where payloads hang on southbridge IO.
Change-Id: Iabb54d9954d442a1a7b48a6c6e76faa8079a4c71 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/i82801gx/early_init.c 1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/36809/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36809 )
Change subject: sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36809 )
Change subject: sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x ......................................................................
sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x
The northbridge code to set up DMI is not correct and the CIR bits relate to that.
This fixes a regression caused by 2437fe9 'sb/intel/i82801gx: Move CIR init to a common place', where payloads hang on southbridge IO.
Change-Id: Iabb54d9954d442a1a7b48a6c6e76faa8079a4c71 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/36809 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Patrick Georgi pgeorgi@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/i82801gx/early_init.c 1 file changed, 4 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 0bd6198..f91a5dc 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -112,6 +112,9 @@ RCBA8(OIC) = 0x03; RCBA8(OIC);
- ich7_setup_cir(); + /* A lot of CIR bits relate DMI setup which is likely not correctly + done for x4x. The issue is also present on ICH10. */ + if (!CONFIG(NORTHBRIDGE_INTEL_X4X)) + ich7_setup_cir(); } #endif
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Patrick Georgi (Code Review)