Attention is currently required from: Hung-Te Lin, Julius Werner.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51620 )
Change subject: soc/mediatek: Use mrc_cache for asurada
......................................................................
Patch Set 4:
(1 comment)
File src/soc/mediatek/mt8192/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/51620/comment/101d051a_bf4c7540
PS3, Line 44: 48K
reduce bootblock by 1kb
0x1000 (0x210000-0x211000) should be 4K.
I wonder if we can add some LD flags to dram-k so it can load on 4k-aligned pages, not 64k aligned?
Actually I don't know why it is now 64K aligned. This conclusion came from my early experiment (with starting address like 0x218000).
--
To view, visit
https://review.coreboot.org/c/coreboot/+/51620
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ief942048ce530433a57e8205d3a68ad56235b427
Gerrit-Change-Number: 51620
Gerrit-PatchSet: 4
Gerrit-Owner: Yu-Ping Wu
yupingso@google.com
Gerrit-Reviewer: Hung-Te Lin
hungte@chromium.org
Gerrit-Reviewer: Julius Werner
jwerner@chromium.org
Gerrit-Reviewer: Xi Chen
xixi.chen@mediatek.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Attention: Hung-Te Lin
hungte@chromium.org
Gerrit-Attention: Julius Werner
jwerner@chromium.org
Gerrit-Comment-Date: Tue, 23 Mar 2021 03:00:31 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Hung-Te Lin
hungte@chromium.org
Gerrit-MessageType: comment