Change in coreboot[master]: soc/intel/denverton_ns: Include microcde

[Felix Singer (Code Review)]

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39266 )

Change subject: soc/intel/denverton_ns: Include microcde
......................................................................

soc/intel/denverton_ns: Include microcde

Signed-off-by: Felix Singer 
Change-Id: Iaa295c74e9c470d5830e22d0b0c73013c7333293
---
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/Makefile.inc
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39266/1

diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index 9a61127..bec149c 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -53,6 +53,7 @@
    select UDELAY_TSC
    select UDK_2015_BINDING
    select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+	select SUPPORT_CPU_UCODE_IN_CBFS

config MMCONF_BASE_ADDRESS
    hex
diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc
index 4050f61..4edcdf4 100644
--- a/src/soc/intel/denverton_ns/Makefile.inc
+++ b/src/soc/intel/denverton_ns/Makefile.inc
@@ -94,4 +94,6 @@
 $(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) --xip
 $(call strip_quotes,$(CONFIG_FSP_S_CBFS))-options := -b $(CONFIG_FSP_S_ADDR) --xip

+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5f-01
+
 endif ## CONFIG_SOC_INTEL_DENVERTON_NS

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39266 )

Change subject: soc/intel/denverton_ns: Include microcde
......................................................................

Patch Set 1: Code-Review+1

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39266 )

Change subject: soc/intel/denverton_ns: Include microcde
......................................................................

Patch Set 1: Code-Review+2

Change in coreboot[master]: soc/intel/denverton_ns: Allow including microcde

[Felix Singer (Code Review)]

Hello build bot (Jenkins), David Guckian, Patrick Georgi, Martin Roth, Vanessa Eusebio, Angel Pons, Michael Niewöhner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39266

to look at the new patch set (#2).

Change subject: soc/intel/denverton_ns: Allow including microcde
......................................................................

soc/intel/denverton_ns: Allow including microcde

Signed-off-by: Felix Singer 
Change-Id: Iaa295c74e9c470d5830e22d0b0c73013c7333293
---
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/Makefile.inc
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39266/2

Change in coreboot[master]: soc/intel/denverton_ns: Allow including microcde

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39266 )

Change subject: soc/intel/denverton_ns: Allow including microcde
......................................................................

Patch Set 2: Code-Review+1

Change in coreboot[master]: soc/intel/denverton_ns: Allow including microcde

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39266 )

Change subject: soc/intel/denverton_ns: Allow including microcde
......................................................................

Patch Set 2: Code-Review+2

Change in coreboot[master]: soc/intel/denverton_ns: Allow including microcde

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39266 )

Change subject: soc/intel/denverton_ns: Allow including microcde
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39266/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39266/2//COMMIT_MSG@7 
PS2, Line 7: microcde
microc*o*de updates

Change in coreboot[master]: soc/intel/denverton_ns: Allow including microcode

[Felix Singer (Code Review)]

Hello build bot (Jenkins), David Guckian, Patrick Georgi, Martin Roth, Paul Menzel, Vanessa Eusebio, Angel Pons, Arthur Heymans, Michael Niewöhner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39266

to look at the new patch set (#3).

Change subject: soc/intel/denverton_ns: Allow including microcode
......................................................................

soc/intel/denverton_ns: Allow including microcode

Signed-off-by: Felix Singer 
Change-Id: Iaa295c74e9c470d5830e22d0b0c73013c7333293
---
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/Makefile.inc
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39266/3

Change in coreboot[master]: soc/intel/denverton_ns: Allow including microcode

[Felix Singer (Code Review)]

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39266 )

Change subject: soc/intel/denverton_ns: Allow including microcode
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39266/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39266/2//COMMIT_MSG@7 
PS2, Line 7: microcde
> microc*o*de updates

Done

Change in coreboot[master]: soc/intel/denverton_ns: Allow including microcode

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39266 )

Change subject: soc/intel/denverton_ns: Allow including microcode
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: soc/intel/denverton_ns: Allow including microcode

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39266 )

Change subject: soc/intel/denverton_ns: Allow including microcode
......................................................................

soc/intel/denverton_ns: Allow including microcode

Signed-off-by: Felix Singer 
Change-Id: Iaa295c74e9c470d5830e22d0b0c73013c7333293
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39266
Reviewed-by: Angel Pons 
Reviewed-by: Paul Menzel 
Reviewed-by: Arthur Heymans 
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/Makefile.inc
2 files changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Arthur Heymans: Looks good to me, approved
  Angel Pons: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index a74250b..23b8452 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -53,6 +53,7 @@
    select UDELAY_TSC
    select UDK_2015_BINDING
    select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+	select SUPPORT_CPU_UCODE_IN_CBFS

config MMCONF_BASE_ADDRESS
    hex
diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc
index 7529892..635dab8 100644
--- a/src/soc/intel/denverton_ns/Makefile.inc
+++ b/src/soc/intel/denverton_ns/Makefile.inc
@@ -92,4 +92,6 @@
 $(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) --xip
 $(call strip_quotes,$(CONFIG_FSP_S_CBFS))-options := -b $(CONFIG_FSP_S_ADDR) --xip

+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5f-01
+
 endif ## CONFIG_SOC_INTEL_DENVERTON_NS

Change in coreboot[master]: soc/intel/denverton_ns: Allow including microcode

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39266 )

Change subject: soc/intel/denverton_ns: Allow including microcode
......................................................................

Patch Set 4:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1124
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1123
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1122

Please note: This test is under development and might not be accurate at all!