Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Singer, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, niehaitao@bytedance.com.
TangYiwei has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75722?usp=email )
Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs ......................................................................
Patch Set 7:
(14 comments)
File src/mainboard/bytedance/Kconfig:
https://review.coreboot.org/c/coreboot/+/75722/comment/0ea2a05b_a0808d5c : PS6, Line 15: config MAINBOARD_FAMILY : default "Family"
This is supposed to be configured in the mainboard Kconfig
Done
File src/mainboard/bytedance/bd_egs/Kconfig:
https://review.coreboot.org/c/coreboot/+/75722/comment/4f3aa1cf_55978cca : PS6, Line 17: string
no need to redefine types, remove
Done
https://review.coreboot.org/c/coreboot/+/75722/comment/218c4850_3ac35972 : PS6, Line 21: string
remove
Done
https://review.coreboot.org/c/coreboot/+/75722/comment/b5b1d8d2_9b253489 : PS6, Line 25: string
remove
Done
https://review.coreboot.org/c/coreboot/+/75722/comment/6ed559f1_66112745 : PS6, Line 29: int
remove
Done
https://review.coreboot.org/c/coreboot/+/75722/comment/7986a559_a4bdb340 : PS6, Line 33: string
remove
Done
File src/mainboard/bytedance/bd_egs/bootblock.c:
https://review.coreboot.org/c/coreboot/+/75722/comment/6b871830_e6ae457b : PS6, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
Some of the files are licensed with GPL-2.0-or-later. […]
Done
File src/mainboard/bytedance/bd_egs/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/75722/comment/0d71ff26_c4aba6a6 : PS6, Line 4: # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
Seems superfluous, please remove
Done
File src/mainboard/bytedance/bd_egs/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/75722/comment/2bef6261_7e1d388d : PS6, Line 14: // platform ACPI tables
Seems superfluous, please remove
Done
https://review.coreboot.org/c/coreboot/+/75722/comment/dc17fd9b_db634f84 : PS6, Line 17: // global NVS and variables
same
Done
https://review.coreboot.org/c/coreboot/+/75722/comment/0a332657_68133db3 : PS6, Line 22: // SPR-SP ACPI tables
same
Done
https://review.coreboot.org/c/coreboot/+/75722/comment/1cd9d3cd_f6f82638 : PS6, Line 25: // LPC related entries
same
Done
File src/mainboard/bytedance/bd_egs/gpio.h:
https://review.coreboot.org/c/coreboot/+/75722/comment/72adc840_4f92ec16 : PS6, Line 4:
Missing header guards
Done
File src/mainboard/bytedance/bd_egs/ramstage.c:
https://review.coreboot.org/c/coreboot/+/75722/comment/c88c27ff_8852507a : PS6, Line 8: void mainboard_silicon_init_params(FSPS_UPD *params) : { : }
remove
Done