Change in coreboot[master]: soc/amd/stoneyridge: factor out early AOAC initialization

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60140 )

Change subject: soc/amd/stoneyridge: factor out early AOAC initialization
......................................................................

soc/amd/stoneyridge: factor out early AOAC initialization

Factor out enable_aoac_devices out of southbridge.c to aoac.c to align
Stoneyridge more with Picasso and Cezanne.

Signed-off-by: Felix Held 
Change-Id: Ied4d821138507639cad1794f6c5017b5873b761f
---
M src/soc/amd/stoneyridge/Makefile.inc
A src/soc/amd/stoneyridge/aoac.c
M src/soc/amd/stoneyridge/southbridge.c
3 files changed, 40 insertions(+), 33 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/60140/1

diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 7d0b86d..9f36b4d 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -4,6 +4,7 @@

subdirs-y += ../../../cpu/amd/mtrr/

+bootblock-y += aoac.c
 bootblock-y += uart.c
 bootblock-y += BiosCallOuts.c
 bootblock-y += bootblock.c
diff --git a/src/soc/amd/stoneyridge/aoac.c b/src/soc/amd/stoneyridge/aoac.c
new file mode 100644
index 0000000..7c1d12d
--- /dev/null
+++ b/src/soc/amd/stoneyridge/aoac.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/aoac.h>
+#include <delay.h>
+#include <soc/aoac_defs.h>
+#include <soc/southbridge.h>
+#include <types.h>
+
+/*
+ * Table of devices that need their AOAC registers enabled and waited
+ * upon (usually about .55 milliseconds). Instead of individual delays
+ * waiting for each device to become available, a single delay will be
+ * executed.
+ */
+static const unsigned int aoac_devs[] = {
+	FCH_AOAC_DEV_UART0 + CONFIG_UART_FOR_CONSOLE * 2,
+	FCH_AOAC_DEV_AMBA,
+	FCH_AOAC_DEV_I2C0,
+	FCH_AOAC_DEV_I2C1,
+	FCH_AOAC_DEV_I2C2,
+	FCH_AOAC_DEV_I2C3,
+};
+
+void enable_aoac_devices(void)
+{
+	bool status;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(aoac_devs); i++)
+		power_on_aoac_device(aoac_devs[i]);
+
+	/* Wait for AOAC devices to indicate power and clock OK */
+	do {
+		udelay(100);
+		status = true;
+		for (i = 0; i < ARRAY_SIZE(aoac_devs); i++)
+			status &= is_aoac_device_enabled(aoac_devs[i]);
+	} while (!status);
+}
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 2ffbc92..a5cbb10 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -23,7 +23,6 @@
 #include <soc/southbridge.h>
 #include <soc/smi.h>
 #include <soc/amd_pci_int_defs.h>
-#include <delay.h>
 #include <soc/pci_devs.h>
 #include <agesa_headers.h>
 #include <soc/acpi.h>
@@ -32,21 +31,6 @@
 #include <soc/nvs.h>
 #include <types.h>

-/*
- * Table of devices that need their AOAC registers enabled and waited
- * upon (usually about .55 milliseconds). Instead of individual delays
- * waiting for each device to become available, a single delay will be
- * executed.
- */
-static const unsigned int aoac_devs[] = {
-	FCH_AOAC_DEV_UART0 + CONFIG_UART_FOR_CONSOLE * 2,
-	FCH_AOAC_DEV_AMBA,
-	FCH_AOAC_DEV_I2C0,
-	FCH_AOAC_DEV_I2C1,
-	FCH_AOAC_DEV_I2C2,
-	FCH_AOAC_DEV_I2C3,
-};
-
 static int is_sata_config(void)
 {
    return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE)
@@ -152,23 +136,6 @@
    return irq_association;
 }

-void enable_aoac_devices(void)
-{
-	bool status;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(aoac_devs); i++)
-		power_on_aoac_device(aoac_devs[i]);
-
-	/* Wait for AOAC devices to indicate power and clock OK */
-	do {
-		udelay(100);
-		status = true;
-		for (i = 0; i < ARRAY_SIZE(aoac_devs); i++)
-			status &= is_aoac_device_enabled(aoac_devs[i]);
-	} while (!status);
-}
-
 static void sb_enable_lpc(void)
 {
    u8 byte;