[S] Change in coreboot[master]: drivers/intel/fsp2_0: Introduce early MRC cache store

[Subrata Banik (Code Review)]

Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Paul Menzel, Raul Rangel, Subrata Banik.

Hello Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nico Huber, Raul Rangel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/77556?usp=email

to look at the new patch set (#4).

Change subject: drivers/intel/fsp2_0: Introduce early MRC cache store
......................................................................

drivers/intel/fsp2_0: Introduce early MRC cache store

This patch refactors the existing MRC cache storing logic, which was
spread between the ROM and RAM stages, into a single early MRC cache
store stage.

It reverts all the logic introduced by commit 7b5a93153a17 (drivers/intel/fsp2_0: Update MRC cache in ramstage) because it is no longer required due to improved memory caching at the pre-RAM phase (with the ramtop implementation). Therefore, the original purpose of doing MRC cache early in ramstage is no longer beneficial, and it is better to do the same operation late in romstage (after RAM initialization).

In this updated logic, the romstage (post FSP-M) will attempt to save
the MRC cache. Depending on whether the MRC_STASH_TO_CBMEM config is
enabled, the MRC cache will either be written directly to NVRAM at the
romstage or stashed into CBMEM for a late NVRAM write at ramstage.

Below table captures the change in the boot state w/ and w/o this
patch for storing the MRC cache. Overall the goal is to ensure the
platform behavior is remain unchanged before and after this patch.

w/o this patch:
+---------------------+--------------------------+--------------------------+-------------------------+
|                     | Save MRC Cache           | Finalize MRC Cache       | Lock the Boot Medium    |
+---------------------+--------------------------+--------------------------+-------------------------+
| MRC_WRITE_NV_LATE   | BS_OS_RESUME_CHECK_ENTRY | BS_OS_RESUME_CHECK_ENTRY | BS_OS_RESUME_CHECK_EXIT |
+---------------------+--------------------------+--------------------------+-------------------------+
| MRC_STASH_TO_CBMEM  | BS_DEV_ENUMERATE_EXIT    | BS_DEV_ENUMERATE_EXIT    | BS_DEV_RESOURCES_ENTRY  |
+---------------------+--------------------------+--------------------------+-------------------------+
| Platform w/o above  | BS_PRE_DEVICE_ENTRY	 | BS_DEV_ENUMERATE_EXIT    | BS_DEV_RESOURCES_ENTRY  |
| configs (FSP 2.0    |                          |                          |                         |
| platforms)          |                          |                          |                         |
+---------------------+--------------------------+--------------------------+-------------------------+

w/ this patch:

+--------------------+--------------------------+--------------------------+-------------------------+
|                    | Save MRC Cache           | Finalize MRC Cache       | Lock the Boot Medium    |
+--------------------+--------------------------+--------------------------+-------------------------+
| MRC_WRITE_NV_LATE  | BS_OS_RESUME_CHECK_ENTRY | BS_OS_RESUME_CHECK_ENTRY | BS_OS_RESUME_CHECK_EXIT |
+--------------------+--------------------------+--------------------------+-------------------------+
| MRC_STASH_TO_CBMEM | BS_DEV_ENUMERATE_EXIT    | BS_DEV_ENUMERATE_EXIT    | BS_DEV_RESOURCES_ENTRY  |
+--------------------+--------------------------+--------------------------+-------------------------+
| Platform w/o above | Post FSP-M (romstage)    | BS_DEV_ENUMERATE_EXIT    | BS_DEV_RESOURCES_ENTRY  |
| configs (FSP 2.0   |                          |                          |                         |
| platforms)         |                          |                          |                         |
+--------------------+--------------------------+--------------------------+-------------------------+

Allows all the FSP2.0 based platform to perform the MRC cache save
operation early from romstage.

BUG=b:296704537
TEST=Able to build and boot google/rex without any boot time impact.

Change-Id: Id1e91d25916594f59d1e467a142f5042c6138b51
Signed-off-by: Subrata Banik 
---
M src/drivers/intel/fsp2_0/memory_init.c
1 file changed, 18 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/77556/4