Attention is currently required from: Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56017 )
Change subject: [WIP]Documentation: Improve x86_64 ......................................................................
Patch Set 1:
(11 comments)
Patchset:
PS1: Thank you for documenting this.
File Documentation/arch/x86/x86_64.md:
https://review.coreboot.org/c/coreboot/+/56017/comment/9420abcb_632522b9 PS1, Line 4: build built
https://review.coreboot.org/c/coreboot/+/56017/comment/9aa3e343_eafe62a6 PS1, Line 5: UEFIs UEFI’s
https://review.coreboot.org/c/coreboot/+/56017/comment/63e51bb4_72204805 PS1, Line 5: only some only runs(?) some
https://review.coreboot.org/c/coreboot/+/56017/comment/34f26b49_53b19037 PS1, Line 5: UEFIs implementation Is that the specification? If not:
some UEFI implementations
https://review.coreboot.org/c/coreboot/+/56017/comment/12d4c3d9_884c6fbd PS1, Line 9: following below
https://review.coreboot.org/c/coreboot/+/56017/comment/f386b2d8_3a178f9c PS1, Line 13: * Intel Sandy Bridge boards Maybe add the `git grep` command to find all boards, or mention the Kconfig symbol?
https://review.coreboot.org/c/coreboot/+/56017/comment/e347423a_afdb846a PS1, Line 22: * The BIOS region is large enough to contain the page tables “BIOS region” refers to Intel hardware, right?
https://review.coreboot.org/c/coreboot/+/56017/comment/0b969b5f_d61bd216 PS1, Line 48: contains contain
https://review.coreboot.org/c/coreboot/+/56017/comment/66a4d238_8a277ee8 PS1, Line 58: It cannot use 32bit addressing as the memory model Please add a dot/period at the end of sentences.
https://review.coreboot.org/c/coreboot/+/56017/comment/b312d193_c53910fb PS1, Line 62: - This requires a complete memory map to be present in postcar stage Ditto.
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Paul Menzel (Code Review)