Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier.
Hello Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83448?usp=email
to look at the new patch set (#5).
Change subject: soc/amd/common/psp_gen2: use MMIO access again ......................................................................
soc/amd/common/psp_gen2: use MMIO access again
Now that we have a get_psp_mmio_base function that will work on all SoCs that use the psp_gen2 code, we can move back to accessing the PSP registers via their MMIO mapping. This sort-of reverts commit 198cc26e4951 ("soc/amd/common/block/psp/psp_gen2: use SMN access to PSP").
Since the first get_psp_mmio_base call in SMM will be done in ramstage when coreboot triggers the APM_CNT_SMMINFO SMI which results in psp_notify_smm being called, the PSP MMIO base address will already be saved to the static variable inside get_psp_mmio_base, so we don't have to worry about get_psp_mmio_base potentially clobbering the SMN index register during OS runtime. Right now, this doesn't matter, since the only PSP mailbox command from the SMI handler after coreboot is done and the OS has taken over will be during the S3/S4/S5 entry which will be triggered by the OS as last step after is done with all its preparations for suspend/shutdown. There will however be future patches that add SMI- handlers that can send PSP mailbox commands during OS runtime where we have to make sure to not clobber the SMN index register.
TEST=PSP mailbox commands are still sent correctly on Mandolin.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I25f16d575991021d65b7b578956d9f90bfd15f6c --- M src/soc/amd/common/block/psp/psb.c M src/soc/amd/common/block/psp/psp_gen2.c 2 files changed, 43 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/83448/5