Venkateswarlu V Vinjamuri has uploaded this change for review. ( https://review.coreboot.org/25638
Change subject: soc/intel/apollolake: Configure PCIe root port #3 for GLK WiFi ......................................................................
soc/intel/apollolake: Configure PCIe root port #3 for GLK WiFi
GLK Octopus uses PCIe root port #3 (PCIe ID 13.0) for discrete PCIe wifi card.
BUG=None BRANCH=None TEST=Use Stone Peak discrete wifi card and test s0ix.
Change-Id: I8a064c5d97e4765bd97ec560c89b207b574b1fa1 Signed-off-by: Venkateswarlu Vinjamuri venkateswarlu.v.vinjamuri@intel.com --- M src/soc/intel/apollolake/acpi/pcie.asl M src/soc/intel/apollolake/chip.c 2 files changed, 11 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/25638/1
diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl index da99591..539ae9b 100644 --- a/src/soc/intel/apollolake/acpi/pcie.asl +++ b/src/soc/intel/apollolake/acpi/pcie.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,3 +22,11 @@
#include "pcie_port.asl" } + +Device (RP03) +{ + Name (_ADR, 0x00130000) + Name (_DDN, "PCIe-A 0") + + #include "pcie_port.asl" +} diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 324fb9f..2c90b48 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -111,6 +111,8 @@ case PCH_DEVFN_SDIO: return "SDIO"; /* PCIe */ + case PCH_DEVFN_PCIE1: + return "RP03"; case PCH_DEVFN_PCIE5: return "RP01"; }