[XS] Change in coreboot[main]: soc/intel/adl: Update DCACHE_BSP_STACK_SIZE

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik.

Hello Dinesh Gehlot, Julius Werner, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/83680?usp=email

to look at the new patch set (#3).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/adl: Update DCACHE_BSP_STACK_SIZE
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soc/intel/adl: Update DCACHE_BSP_STACK_SIZE

During the stages which use Cache-as-RAM (CAR), coreboot needs more than
1 KiB as configured in DCACHE_BSP_STACK_SIZE. After studying the UPDs
for various SoCs(ADL-P, ADL-N, RPL), coreboot stack requirement is
estimated to be 32 KiB. Update DCACHE_BSP_STACK_SIZE accordingly.

BUG=None
TEST=Build Brox BIOS image and boot to OS.

Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/83680/3