Change in coreboot[master]: mb/google/brya/var/taeko: Fix PLD group order(WR)

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Kevin Chang, YH Lin.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59973 )

Change subject: mb/google/brya/var/taeko: Fix PLD group order(WR)
......................................................................

Patch Set 2:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/59973/comment/1f622dfe_5daf4407 
PS2, Line 7: (WR)
sorry, I don't understand what `(WR)` means ?

https://review.coreboot.org/c/coreboot/+/59973/comment/de6e4eee_6a019c53 
PS2, Line 9: In ec/google/chromeec: Add PLD to EC conn in ACPI
           : table(667471b8d807da5a5a9277db47e069ad3b1351c7),
           : PLD is added to ACPI table. It causes the DUT to
           : not boot into the OS. So fix the USB3/USB2 Type-C
           : Port C2 PLD group order from 3 to 2 to solve this
           : issue.
commit messages are 72 characters wide