Change in coreboot[master]: src/*: Update makefiles to exclude x86 code from non-x86 verstage
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ......................................................................
src/*: Update makefiles to exclude x86 code from non-x86 verstage
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP.
BUG=b:158124527 TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I797b67394825172bd44ad1ee693a0c509289486b --- M src/arch/x86/Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/pae/Makefile.inc M src/cpu/x86/tsc/Makefile.inc M src/drivers/pc80/pc/Makefile.inc M src/soc/amd/common/block/acpi/Makefile.inc M src/soc/amd/common/block/alink/Makefile.inc M src/soc/amd/common/block/pci/Makefile.inc 9 files changed, 58 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42062/1
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 0dd8d2b..6446043 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -83,32 +83,24 @@ endef
############################################################################### -# all (bootblock,verstage,romstage,postcar,ramstage) -############################################################################### - -ifeq ($(CONFIG_ARCH_X86),y) - -all-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c -all-y += boot.c -all-y += memcpy.c -all-y += memset.c -all-y += cpu_common.c -all-y += post.c - -endif - -############################################################################### # bootblock ###############################################################################
ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
+bootblock-y += boot.c +bootblock-y += post.c +bootblock-y += cpu_common.c bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S +bootblock-y += memcpy.c +bootblock-y += memset.c bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c bootblock-y += id.S +bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c + $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
bootblock-y += bootblock_crt0.S @@ -129,10 +121,16 @@
ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
+verstage-y += boot.c +verstage-y += post.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += gdt_init.S verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S +verstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
+verstage-y += cpu_common.c +verstage-y += memset.c +verstage-y += memcpy.c verstage-y += memmove.c verstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c # If verstage is a separate stage it means there's no need @@ -161,16 +159,22 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c +romstage-y += boot.c +romstage-y += post.c # gdt_init.S is included by entry32.inc when romstage is the first C # environment. romstage-y += gdt_init.S romstage-y += cbmem.c +romstage-y += cpu_common.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S +romstage-y += memcpy.c romstage-y += memmove.c +romstage-y += memset.c romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c romstage-y += postcar_loader.c romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c +romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c) romstage-libs ?= @@ -196,15 +200,21 @@ postcar-generic-ccopts += -D__POSTCAR__
postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c +postcar-y += boot.c +postcar-y += post.c postcar-y += gdt_init.S +postcar-y += cpu_common.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S postcar-y += exit_car.S +postcar-y += memcpy.c postcar-y += memmove.c +postcar-y += memset.c postcar-y += memlayout.ld postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c postcar-y += postcar.c postcar-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c +postcar-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
LDFLAGS_postcar += -Map $(objcbfs)/postcar.map
@@ -229,15 +239,20 @@
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c +ramstage-y += boot.c +ramstage-y += post.c ramstage-y += c_start.S ramstage-y += cpu.c +ramstage-y += cpu_common.c ramstage-y += ebda.c ramstage-y += exception.c ramstage-y += idt.S ramstage-y += gdt.c ramstage-$(CONFIG_IOAPIC) += ioapic.c +ramstage-y += memcpy.c ramstage-y += memlayout.ld ramstage-y += memmove.c +ramstage-y += memset.c ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c @@ -248,6 +263,7 @@ ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S ramstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S +ramstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) rmodules_x86_32-y += memcpy.c diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 0d11478..a35433e 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -6,7 +6,9 @@ ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c bootblock-y += boot_cpu.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-y += boot_cpu.c +endif romstage-y += boot_cpu.c ramstage-y += boot_cpu.c postcar-y += boot_cpu.c diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 129d05d..3a5ba88 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -2,7 +2,10 @@
romstage-y += earlymtrr.c bootblock-y += earlymtrr.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-y += earlymtrr.c +verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c +endif
bootblock-y += debug.c romstage-y += debug.c @@ -10,4 +13,3 @@ ramstage-y += debug.c
bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c -verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c diff --git a/src/cpu/x86/pae/Makefile.inc b/src/cpu/x86/pae/Makefile.inc index 62176d2..7825db8 100644 --- a/src/cpu/x86/pae/Makefile.inc +++ b/src/cpu/x86/pae/Makefile.inc @@ -1,5 +1,7 @@ bootblock-y += pgtbl.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-y += pgtbl.c +endif romstage-y += pgtbl.c postcar-y += pgtbl.c ramstage-y += pgtbl.c diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index b3925b5..d8f44d9 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,6 +1,8 @@ bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +endif postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 67c40a1..e591dd1 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -7,7 +7,9 @@ romstage-$(CONFIG_SPKMODEM) += spkmodem.c
bootblock-y += i8254.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-y += i8254.c +endif romstage-y += i8254.c ramstage-y += i8254.c postcar-y += i8254.c diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index 708631a..27876aa 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -1,5 +1,7 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c +endif romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c diff --git a/src/soc/amd/common/block/alink/Makefile.inc b/src/soc/amd/common/block/alink/Makefile.inc index 720a7cb..e9d8612 100644 --- a/src/soc/amd/common/block/alink/Makefile.inc +++ b/src/soc/amd/common/block/alink/Makefile.inc @@ -1,5 +1,7 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +endif romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 558a7ac..c5568d4 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,4 +1,14 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y)
-ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c +ramstage-y += amd_pci_util.c
-all-y += amd_pci_mmconf.c +bootblock-y += amd_pci_mmconf.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) +verstage-y += amd_pci_mmconf.c +endif +romstage-y += amd_pci_mmconf.c +postcar-y += amd_pci_mmconf.c +ramstage-y += amd_pci_mmconf.c +smm-y += amd_pci_mmconf.c + +endif
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ......................................................................
Patch Set 1:
Could you make arch/x86/Makefile.inc a separate change?
I believe we would want to make a fundamental decision that any ARCH_xxx guard together with all-y is banned.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ......................................................................
Patch Set 1:
Patch Set 1:
Could you make arch/x86/Makefile.inc a separate change?
I believe we would want to make a fundamental decision that any ARCH_xxx guard together with all-y is banned.
Sure, I can break that out.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ......................................................................
Patch Set 2: Code-Review+1
Need to fix the build failures: /home/coreboot/slave-root/workspace/coreboot-gerrit/src/drivers/amd/agesa/bootblock.c:29: undefined reference to `enable_pci_mmconf'
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ......................................................................
Patch Set 2:
This is going to become a maintenance burden longterm, cluttering Makefiles with preprocessor use. Please file a new bug if you decide to submit this in the shape of patchset #2. I think somwone really has to revisit the build-classes generator to properly support stages running on different arch.
You guarded selected verstage-y under cpu/x86 but you should guard them all. Like drivers/uart too that contains both PCI configuration and IO accesses.
Also picasso/tsc_freq.c is clearly x86-only and does not belong to verstage then.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ......................................................................
Patch Set 2:
Patch Set 2:
This is going to become a maintenance burden longterm, cluttering Makefiles with preprocessor use. Please file a new bug if you decide to submit this in the shape of patchset #2. I think somwone really has to revisit the build-classes generator to properly support stages running on different arch.
You guarded selected verstage-y under cpu/x86 but you should guard them all. Like drivers/uart too that contains both PCI configuration and IO accesses.
Also picasso/tsc_freq.c is clearly x86-only and does not belong to verstage then.
I think rearchitecting the build-class generator for 9 makefiles (3 of which are in amd common) might be overkill.
I'll take a look at tsc_freq. I'm still working on the tsc code portion of the psp.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
This is going to become a maintenance burden longterm, cluttering Makefiles with preprocessor use. Please file a new bug if you decide to submit this in the shape of patchset #2. I think somwone really has to revisit the build-classes generator to properly support stages running on different arch.
You guarded selected verstage-y under cpu/x86 but you should guard them all. Like drivers/uart too that contains both PCI configuration and IO accesses.
Also picasso/tsc_freq.c is clearly x86-only and does not belong to verstage then.
I think rearchitecting the build-class generator for 9 makefiles (3 of which are in amd common) might be overkill.
Well you missed some makefiles already. At least drivers/uart and CONFIG(PCI) section under device/. Any new file added to verstage-y in common code has potential to break picasso build, unless those guards are added. Thus my wording, longterm maintenance burden.
Any verstage-y addition with <device/pci.h> or <arch/io.h> or <cpu/x86/xxx.h> in its includes is invalid for building into PSP. I think it's the right time for a proper fix to support build of stages on different arch.
I'll take a look at tsc_freq. I'm still working on the tsc code portion of the psp.
There was an initiative to re-define both udelay() and timestamp_get() running on top of monotonic timer.
Hello build bot (Jenkins), Nico Huber, Raul Rangel, Patrick Georgi, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42062
to look at the new patch set (#3).
Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ......................................................................
src/*: Update makefiles to exclude x86 code from non-x86 verstage
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP.
BUG=b:158124527 TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I797b67394825172bd44ad1ee693a0c509289486b --- M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/pae/Makefile.inc M src/cpu/x86/tsc/Makefile.inc M src/drivers/pc80/pc/Makefile.inc M src/lib/Makefile.inc M src/soc/amd/common/block/acpi/Makefile.inc M src/soc/amd/common/block/alink/Makefile.inc M src/soc/amd/common/block/pci/Makefile.inc 9 files changed, 29 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42062/3
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ......................................................................
Patch Set 3:
For some reason, there are platforms using files in the common pci directory that don't have CONFIG_SOC_AMD_COMMON_BLOCK_PCI set. That seems like a bug. I'll work on that tomorrow.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42062/3/src/drivers/pc80/pc/Makefil... File src/drivers/pc80/pc/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/3/src/drivers/pc80/pc/Makefil... PS3, Line 11: verstage-y += i8254.c Can we come up with a syntax something like:
verstage-x86_32-y += i8254.c
And at top-level:
verstage-y += verstage-$(ARCH-VERSTAGE-y)-y
That would achieve the same thing but with much less noise.
https://review.coreboot.org/c/coreboot/+/42062/3/src/lib/Makefile.inc File src/lib/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/3/src/lib/Makefile.inc@50 PS3, Line 50: verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c Anything in lib/ should be arch-agnostic. What was the build failure? I would rather just have stub get_timestamp() if there is no good timebase.
https://review.coreboot.org/c/coreboot/+/42062/3/src/soc/amd/common/block/pc... File src/soc/amd/common/block/pci/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/3/src/soc/amd/common/block/pc... PS3, Line 4: endif here should fix it
Maybe the placement of amd_pci_mmconf.c in this directory is a bit unfortunate.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42062/3/src/drivers/pc80/pc/Makefil... File src/drivers/pc80/pc/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/3/src/drivers/pc80/pc/Makefil... PS3, Line 11: verstage-y += i8254.c
Can we come up with a syntax something like: […]
That seems reasonable. I think we need an intermediate value, something like verstage-x86_32_64-y, that evaluates as true for both x86_32 and x86_64, but that's not a big issue.
https://review.coreboot.org/c/coreboot/+/42062/3/src/lib/Makefile.inc File src/lib/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/3/src/lib/Makefile.inc@50 PS3, Line 50: verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
Anything in lib/ should be arch-agnostic. […]
Yeah, this is temporary. I can add a TODO to remove it once I have the timestamps implemented.
https://review.coreboot.org/c/coreboot/+/42062/3/src/soc/amd/common/block/pc... File src/soc/amd/common/block/pci/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/3/src/soc/amd/common/block/pc... PS3, Line 4:
endif here should fix it […]
Agreed, but I think we should probably split this into two directories or control it with two separate options or something.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42062/3/src/drivers/pc80/pc/Makefil... File src/drivers/pc80/pc/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/3/src/drivers/pc80/pc/Makefil... PS3, Line 11: verstage-y += i8254.c
That seems reasonable. […]
Ya. That sounds like a good solution.
Hello build bot (Jenkins), Nico Huber, Raul Rangel, Patrick Georgi, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42062
to look at the new patch set (#4).
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
src/*: Update makefiles to exclude x86 code from psp-verstage
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP.
This change will add these files to verstage only if the verstage architecture is X86 - either 32 or 64 bit.
BUG=b:158124527 TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I797b67394825172bd44ad1ee693a0c509289486b --- M Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/pae/Makefile.inc M src/cpu/x86/tsc/Makefile.inc M src/drivers/pc80/pc/Makefile.inc M src/soc/amd/common/block/acpi/Makefile.inc M src/soc/amd/common/block/alink/Makefile.inc M src/soc/amd/common/block/pci/Makefile.inc 9 files changed, 25 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42062/4
Hello build bot (Jenkins), Nico Huber, Raul Rangel, Patrick Georgi, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42062
to look at the new patch set (#5).
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
src/*: Update makefiles to exclude x86 code from psp-verstage
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP.
This change will add these files to verstage only if the verstage architecture is X86 - either 32 or 64 bit.
BUG=b:158124527 TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I797b67394825172bd44ad1ee693a0c509289486b --- M Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/pae/Makefile.inc M src/cpu/x86/tsc/Makefile.inc M src/drivers/pc80/pc/Makefile.inc M src/soc/amd/common/block/acpi/Makefile.inc M src/soc/amd/common/block/alink/Makefile.inc M src/soc/amd/common/block/pci/Makefile.inc 9 files changed, 21 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42062/5
Hello build bot (Jenkins), Nico Huber, Raul Rangel, Patrick Georgi, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42062
to look at the new patch set (#6).
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
src/*: Update makefiles to exclude x86 code from psp-verstage
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP.
This change will add these files to verstage only if the verstage architecture is X86 - either 32 or 64 bit.
BUG=b:158124527 TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I797b67394825172bd44ad1ee693a0c509289486b --- M Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/pae/Makefile.inc M src/cpu/x86/tsc/Makefile.inc M src/drivers/pc80/pc/Makefile.inc M src/soc/amd/common/block/acpi/Makefile.inc M src/soc/amd/common/block/alink/Makefile.inc M src/soc/amd/common/block/pci/Makefile.inc 9 files changed, 21 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42062/6
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42062/6/Makefile.inc File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/6/Makefile.inc@104 PS6, Line 104: x86_verstage Can you do verstage_x86 instead? I'm assuming you will add a verstage_arm next.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
Patch Set 6:
(6 comments)
https://review.coreboot.org/c/coreboot/+/42062/4/Makefile.inc File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/4/Makefile.inc@616 PS4, Line 616: : ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) : verstage-y += $(verstage-x86_32_64-y) : endif Left over from an earlier version. Will remove.
https://review.coreboot.org/c/coreboot/+/42062/6/Makefile.inc File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/6/Makefile.inc@104 PS6, Line 104: x86_verstage
Can you do verstage_x86 instead? I'm assuming you will add a verstage_arm next.
Sure, I can update it.
I'm not planning on doing a verstage_arm class. There's no need for it yet.
https://review.coreboot.org/c/coreboot/+/42062/3/src/drivers/pc80/pc/Makefil... File src/drivers/pc80/pc/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/3/src/drivers/pc80/pc/Makefil... PS3, Line 11: verstage-y += i8254.c
Ya. That sounds like a good solution.
Done
https://review.coreboot.org/c/coreboot/+/42062/3/src/lib/Makefile.inc File src/lib/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/3/src/lib/Makefile.inc@50 PS3, Line 50: verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
Yeah, this is temporary. I can add a TODO to remove it once I have the timestamps implemented.
Moved to a different commit with a TODO added.
https://review.coreboot.org/c/coreboot/+/42062/4/src/soc/amd/common/block/al... File src/soc/amd/common/block/alink/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/4/src/soc/amd/common/block/al... PS4, Line 2: $(eval $(call verstage-x86,$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK),alink.c)) Didn't get updated with the latest version.
https://review.coreboot.org/c/coreboot/+/42062/3/src/soc/amd/common/block/pc... File src/soc/amd/common/block/pci/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/3/src/soc/amd/common/block/pc... PS3, Line 4:
Agreed, but I think we should probably split this into two directories or control it with two separa […]
Fixed just in this directory for now.
Hello build bot (Jenkins), Raul Rangel, Nico Huber, Patrick Georgi, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42062
to look at the new patch set (#7).
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
src/*: Update makefiles to exclude x86 code from psp-verstage
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP.
This change will add these files to verstage only if the verstage architecture is X86 - either 32 or 64 bit.
BUG=b:158124527 TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I797b67394825172bd44ad1ee693a0c509289486b --- M Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/pae/Makefile.inc M src/cpu/x86/tsc/Makefile.inc M src/drivers/pc80/pc/Makefile.inc M src/soc/amd/common/block/acpi/Makefile.inc M src/soc/amd/common/block/alink/Makefile.inc M src/soc/amd/common/block/pci/Makefile.inc 9 files changed, 21 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42062/7
Hello build bot (Jenkins), Raul Rangel, Nico Huber, Patrick Georgi, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42062
to look at the new patch set (#8).
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
src/*: Update makefiles to exclude x86 code from psp-verstage
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP.
This change will add these files to verstage only if the verstage architecture is X86 - either 32 or 64 bit.
BUG=b:158124527 TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I797b67394825172bd44ad1ee693a0c509289486b --- M Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/pae/Makefile.inc M src/cpu/x86/tsc/Makefile.inc M src/drivers/pc80/pc/Makefile.inc M src/soc/amd/common/block/acpi/Makefile.inc M src/soc/amd/common/block/alink/Makefile.inc M src/soc/amd/common/block/pci/Makefile.inc 9 files changed, 20 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42062/8
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
Patch Set 8:
Every verstage-y file with <arch/io.h> in its build dependencies is wrong.
build/verstage/drivers/pc80/rtc/mc146818rtc_boot.d
I am jumping to conclusion patchset #8 is not build-tested with enabled psp-verstage?
I expect the build to fail again with CMOS_POST=y or OPTION_TABLE=y
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
Patch Set 8:
Patch Set 8:
Every verstage-y file with <arch/io.h> in its build dependencies is wrong.
build/verstage/drivers/pc80/rtc/mc146818rtc_boot.d
I am jumping to conclusion patchset #8 is not build-tested with enabled psp-verstage?
I expect the build to fail again with CMOS_POST=y or OPTION_TABLE=y
It's all tested.
psp_verstage supplies its own arch/io.h https://review.coreboot.org/c/coreboot/+/41816/5/src/soc/amd/picasso/psp_ver...
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
Patch Set 9:
(2 comments)
Patch Set 8:
Patch Set 8:
Every verstage-y file with <arch/io.h> in its build dependencies is wrong.
build/verstage/drivers/pc80/rtc/mc146818rtc_boot.d
I am jumping to conclusion patchset #8 is not build-tested with enabled psp-verstage?
I expect the build to fail again with CMOS_POST=y or OPTION_TABLE=y
It's all tested.
psp_verstage supplies its own arch/io.h https://review.coreboot.org/c/coreboot/+/41816/5/src/soc/amd/picasso/psp_ver...
Right, my bad. I did not expect that because it was not mentioned in the commit message. Providing include overrides for <arch/x> looks somewhat unorthodox but if it gets you one step further. I'll comment there in CB:41816.
Also nobody brought this up in CB:42183 or CB:42416, where I put ENV_X86 around <arch/io.h>. Looks like ENV_HAS_ARCH_IO should be introduced into <rules.h> then.
https://review.coreboot.org/c/coreboot/+/42062/9/src/cpu/x86/lapic/Makefile.... File src/cpu/x86/lapic/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/9/src/cpu/x86/lapic/Makefile.... PS9, Line 9: verstage_x86-y += boot_cpu.c I hope the syntax is expanded, some day, such that we have "all_x86-y += " for cases like these. Even better, if every "bootblock-y +=" under cpu/x86/ would be automatically treated as "bootblock_x86-y +=" since that is ultimately what we need here.
https://review.coreboot.org/c/coreboot/+/42062/9/src/drivers/pc80/pc/Makefil... File src/drivers/pc80/pc/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/9/src/drivers/pc80/pc/Makefil... PS9, Line 10: verstage_x86-y += i8254.c So it's excluded because it has inline asm? Not because of <arch/io.h>. This means my reasoning for CB:42221 changes to pc80/rtc/Makefile.inc were incorrect.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42062/9/src/cpu/x86/lapic/Makefile.... File src/cpu/x86/lapic/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/9/src/cpu/x86/lapic/Makefile.... PS9, Line 9: verstage_x86-y += boot_cpu.c
I hope the syntax is expanded, some day, such that we have "all_x86-y += " for cases like these. […]
Sure, I think that's a nice-to-have.
https://review.coreboot.org/c/coreboot/+/42062/9/src/drivers/pc80/pc/Makefil... File src/drivers/pc80/pc/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/9/src/drivers/pc80/pc/Makefil... PS9, Line 10: verstage_x86-y += i8254.c
So it's excluded because it has inline asm? Not because of <arch/io.h>. […]
Yes, it's because of the inline asm.
Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
Patch Set 10: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42062/9/src/drivers/pc80/pc/Makefil... File src/drivers/pc80/pc/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/9/src/drivers/pc80/pc/Makefil... PS9, Line 10: verstage_x86-y += i8254.c
Yes, it's because of the inline asm.
Martin - the inline assembly also has access to timers which are not present afaik on the PSP right? So including this doesn't make sense and requires a different PSP library.
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
Patch Set 10: Code-Review+1
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
Patch Set 11: Code-Review+2
(3 comments)
https://review.coreboot.org/c/coreboot/+/42062/4/Makefile.inc File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/4/Makefile.inc@616 PS4, Line 616: : ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) : verstage-y += $(verstage-x86_32_64-y) : endif
Left over from an earlier version. Will remove.
Done
https://review.coreboot.org/c/coreboot/+/42062/6/Makefile.inc File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/6/Makefile.inc@104 PS6, Line 104: x86_verstage
Sure, I can update it. […]
Done
https://review.coreboot.org/c/coreboot/+/42062/4/src/soc/amd/common/block/al... File src/soc/amd/common/block/alink/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42062/4/src/soc/amd/common/block/al... PS4, Line 2: $(eval $(call verstage-x86,$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK),alink.c))
Didn't get updated with the latest version.
Done
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from psp-verstage ......................................................................
src/*: Update makefiles to exclude x86 code from psp-verstage
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP.
This change will add these files to verstage only if the verstage architecture is X86 - either 32 or 64 bit.
BUG=b:158124527 TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I797b67394825172bd44ad1ee693a0c509289486b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062 Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Eric Peers epeers@google.com Reviewed-by: Rob Barnes robbarnes@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/pae/Makefile.inc M src/cpu/x86/tsc/Makefile.inc M src/drivers/pc80/pc/Makefile.inc M src/soc/amd/common/block/acpi/Makefile.inc M src/soc/amd/common/block/alink/Makefile.inc M src/soc/amd/common/block/pci/Makefile.inc 9 files changed, 20 insertions(+), 9 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Eric Peers: Looks good to me, but someone else must approve Rob Barnes: Looks good to me, but someone else must approve
diff --git a/Makefile.inc b/Makefile.inc index 86335d9..7f61a5e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -99,6 +99,13 @@ $(call add-special-class,all) all-handler = $(foreach class,bootblock verstage romstage postcar ramstage,$(eval $(class)-y += $(2)))
+$(call add-special-class,verstage_x86) +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) +verstage_x86-handler = $(eval verstage-y += $(2)) +else +verstage_x86-handler = +endif + # Add dynamic classes for rmodules $(foreach supported_arch,$(ARCH_SUPPORTED), \ $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch)))) diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 0d11478..ea16014 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -6,7 +6,7 @@ ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c bootblock-y += boot_cpu.c -verstage-y += boot_cpu.c +verstage_x86-y += boot_cpu.c romstage-y += boot_cpu.c ramstage-y += boot_cpu.c postcar-y += boot_cpu.c diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 129d05d..3f33e31 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -2,7 +2,7 @@
romstage-y += earlymtrr.c bootblock-y += earlymtrr.c -verstage-y += earlymtrr.c +verstage_x86-y += earlymtrr.c
bootblock-y += debug.c romstage-y += debug.c @@ -10,4 +10,4 @@ ramstage-y += debug.c
bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c -verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c +verstage_x86-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c diff --git a/src/cpu/x86/pae/Makefile.inc b/src/cpu/x86/pae/Makefile.inc index 62176d2..70e0b2f 100644 --- a/src/cpu/x86/pae/Makefile.inc +++ b/src/cpu/x86/pae/Makefile.inc @@ -1,5 +1,5 @@ bootblock-y += pgtbl.c -verstage-y += pgtbl.c +verstage_x86-y += pgtbl.c romstage-y += pgtbl.c postcar-y += pgtbl.c ramstage-y += pgtbl.c diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index b3925b5..a0cd145 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,6 +1,6 @@ bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c -verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +verstage_x86-$(CONFIG_UDELAY_TSC) += delay_tsc.c postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 67c40a1..63ed998 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -7,7 +7,7 @@ romstage-$(CONFIG_SPKMODEM) += spkmodem.c
bootblock-y += i8254.c -verstage-y += i8254.c +verstage_x86-y += i8254.c romstage-y += i8254.c ramstage-y += i8254.c postcar-y += i8254.c diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index 708631a..f0b336d 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -1,5 +1,5 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c -verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c +verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c diff --git a/src/soc/amd/common/block/alink/Makefile.inc b/src/soc/amd/common/block/alink/Makefile.inc index 720a7cb..9d27aec 100644 --- a/src/soc/amd/common/block/alink/Makefile.inc +++ b/src/soc/amd/common/block/alink/Makefile.inc @@ -1,5 +1,5 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c -verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 558a7ac..baebb6c 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,4 +1,8 @@
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c
-all-y += amd_pci_mmconf.c +bootblock-y += amd_pci_mmconf.c +verstage_x86-y += amd_pci_mmconf.c +romstage-y += amd_pci_mmconf.c +postcar-y += amd_pci_mmconf.c +ramstage-y += amd_pci_mmconf.c
-
Aaron Durbin (Code Review) -
Eric Peers (Code Review)
-
Felix Held (Code Review)
-
Kyösti Mälkki (Code Review)
-
Martin Roth (Code Review)
-
Raul Rangel (Code Review)
-
Rob Barnes (Code Review)