[S] Change in coreboot[main]: [TEST]soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS

[Ravishankar Sarawadi (Code Review)]

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun.

Hello Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/78163?usp=email

to look at the new patch set (#2).

Change subject: [TEST]soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
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[TEST]soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS

Within TBT PCIe, follwing register offsets have been updated for
production silicon. Update ASL with new offsets.
1. MPC - Miscellaneous Port Configuration Register
2. RPPGEN - Root Port Power Gating Enable
3. SMSCS - SMI/SCI Status Register

TEST= Check TBT PCIe Tunnnel creation and device enumration.
Change-Id: I0497f7108ef5046c2694aece232263582514a0c5
Signed-off-by: Ravi Sarawadi 
---
M src/soc/intel/meteorlake/acpi/tcss_pcierp.asl
1 file changed, 16 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/78163/2