Change in coreboot[master]: soc/intel/cannonlake: Add DisableHeciRetry to config

[Christian Walter (Code Review)]

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40756 )

Change subject: soc/intel/cannonlake: Add DisableHeciRetry to config
......................................................................

soc/intel/cannonlake: Add DisableHeciRetry to config

Add DisableHeciRetry to the chip config and parse it in romstage.

Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf
Signed-off-by: Christian Walter 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/40756/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 578473b..981c381 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -195,6 +195,7 @@

/* Heci related */
    uint8_t Heci3Enabled;
+	uint8_t DisableHeciRetry;

/* Gfx related */
    uint8_t IgdDvmt50PreAlloc;
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 010d152c..c99f5a5 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -128,6 +128,8 @@
    			config->sata_port[i].TxGen3DeEmph;
    	}
    }
+	if (config->DisableHeciRetry)
+		tconfig->DisableHeciRetry = config->DisableHeciRetry;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

[Christian Walter (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40756

to look at the new patch set (#2).

Change subject: soc/intel/cannonlake: Add DisableHeciRetry to config
......................................................................

soc/intel/cannonlake: Add DisableHeciRetry to config

Add DisableHeciRetry to the chip config and parse it in romstage.

Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf
Signed-off-by: Christian Walter 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/40756/2

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40756 )

Change subject: soc/intel/cannonlake: Add DisableHeciRetry to config
......................................................................

Patch Set 2: Code-Review+2

[Patrick Rudolph (Code Review)]

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40756 )

Change subject: soc/intel/cannonlake: Add DisableHeciRetry to config
......................................................................

soc/intel/cannonlake: Add DisableHeciRetry to config

Add DisableHeciRetry to the chip config and parse it in romstage.

Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf
Signed-off-by: Christian Walter 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756
Tested-by: build bot (Jenkins) 
Reviewed-by: Philipp Deppenwiese 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 5 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Philipp Deppenwiese: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index b74291e..d4d76cd 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -194,6 +194,7 @@

/* Heci related */
    uint8_t Heci3Enabled;
+	uint8_t DisableHeciRetry;

/* Gfx related */
    uint8_t IgdDvmt50PreAlloc;
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 010d152c..7af90a7 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -128,6 +128,10 @@
    			config->sata_port[i].TxGen3DeEmph;
    	}
    }
+#if !CONFIG(SOC_INTEL_COMETLAKE)
+	if (config->DisableHeciRetry)
+		tconfig->DisableHeciRetry = config->DisableHeciRetry;
+#endif
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40756 )

Change subject: soc/intel/cannonlake: Add DisableHeciRetry to config
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Patch Set 5:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3183
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3182
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3181
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3180

Please note: This test is under development and might not be accurate at all!