Attention is currently required from: Arthur Heymans, Nico Huber, Martin Roth, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Felix Held. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )
Change subject: soc/intel/elkhartlake: Introduce Intel PSE ......................................................................
Patch Set 53:
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55367/comment/58c47f3e_11931e8a PS52, Line 23: it's
its
Done
https://review.coreboot.org/c/coreboot/+/55367/comment/2e0e6a01_01b1d4a9 PS52, Line 27: locate
locates the
Done
https://review.coreboot.org/c/coreboot/+/55367/comment/29849d4d_9a72de7c PS52, Line 30: enables
enable
Done
https://review.coreboot.org/c/coreboot/+/55367/comment/9302ac2b_7c87ad9e PS52, Line 32: These assignments
Exactly one space please.
Done
https://review.coreboot.org/c/coreboot/+/55367/comment/b0c36e24_bffa3456 PS52, Line 9: The Intel® Programmable Services Engine (Intel® PSE) is a : dedicated offload engine for IoT functions powered by an ARM : Cortex-M7 microcontroller. It provides independent, low-DMIPS : computing and low-speed I/Os for IoT applications, plus : dedicated services for real-time computing and time-sensitive : synchronization. : : The PSE hosts new functions, including remote out-of-band : device management, network proxy, embedded controller lite : and sensor hub. : : This CL enables the user to provide the base address of the : PSE FW blob which will then be loaded by the FSP-S onto the : ARM controller. PSE FW will do the initialization work of : PSE controller and it's peripherals. The loading of PSE FW : should have negligible impact on boot time unless PSE : controller could not locate PSE FW and FSP will attempt to : redo PSE FW loading and wait for PSE handshake until it times : out. Once PSE controller locate PSE FW, it will do initialization : concurrently by itself with coreboot booting. : : It also adds PSE related FSP-S UPD settings which enables the : setup of peripheral ownership (assigned to the PSE or x86 : subsystem) and interrupts. These assignments need to take : place at a given point in the boot process and cannot be : changed later. : : To verify if PSE FW is loaded properly, the user could enable : PchPseShellEnabled flag and the log will be printed at PSE UART 2. : : For further info please refer to doc #611825 (for HW overview) : and #614110 (for PSE EDS).
Yes, 72 characters is the preferred length. […]
Done
File src/soc/intel/elkhartlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/55367/comment/caf5be89_723c771f PS52, Line 202: atom
nit: Capitalize `Atom`
Done
https://review.coreboot.org/c/coreboot/+/55367/comment/bb8a7e4d_ea5b22be PS52, Line 212: c
typo: remove extra `c` in `ex*ecuted`
Done
File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/55367/comment/f0db3ed6_6357c0f9 PS52, Line 94: %08x
You can use `z` to print a `size_t` variable without any casts. […]
This is brilliant, didnt know that! Thanks Angel.
-
Lean Sheng Tan (Code Review)