[XS] Change in coreboot[main]: tree: use boolean for hybrid_storage_mode

[Elyes Haouas (Code Review)]

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84157?usp=email )

Change subject: tree: use boolean for hybrid_storage_mode
......................................................................

tree: use boolean for hybrid_storage_mode

Change-Id: I84aad5497d17065f9d42776452f2d2d24cd50a91
Signed-off-by: Elyes Haouas 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84157
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
---
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/msi/ms7d25/devicetree.cb
M src/mainboard/msi/ms7e06/devicetree.cb
4 files changed, 4 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 95b006e..a6bad13 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -83,7 +83,7 @@
    }"

# Hybrid storage mode
-	register "hybrid_storage_mode" = "1"
+	register "hybrid_storage_mode" = "true"

# Enable CPU PCIE RP 1 using CLK 0
    register "cpu_pcie_rp[CPU_RP(1)]" = "{
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 0b3a3ef..922b673 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -76,7 +76,7 @@
    }"

# Hybrid storage mode
-	register "hybrid_storage_mode" = "1"
+	register "hybrid_storage_mode" = "true"

# Enable CPU PCIE RP 1 using CLK 0
    register "cpu_pcie_rp[CPU_RP(1)]" = "{
diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb
index e874679..d22cd92 100644
--- a/src/mainboard/msi/ms7d25/devicetree.cb
+++ b/src/mainboard/msi/ms7d25/devicetree.cb
@@ -82,7 +82,7 @@
    	[DDI_PORT_4] = DDI_ENABLE_HPD,
    }"

-	register "hybrid_storage_mode" = "1"
+	register "hybrid_storage_mode" = "true"
    register "dmi_power_optimize_disable" = "1"

# FIVR configuration
diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb
index 738c8a3..298e9b0 100644
--- a/src/mainboard/msi/ms7e06/devicetree.cb
+++ b/src/mainboard/msi/ms7e06/devicetree.cb
@@ -12,7 +12,7 @@
    register "pmc_gpe0_dw1" = "GPP_VPGIO"
    register "pmc_gpe0_dw2" = "GPD"

-	register "hybrid_storage_mode" = "1"
+	register "hybrid_storage_mode" = "true"
    register "dmi_power_optimize_disable" = "1"

# FIVR configuration