[M] Change in coreboot[main]: mb/system76/oryp5/dt: Make use of chipset devicetree

[Felix Singer (Code Review)]

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78839?usp=email )

(

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/system76/oryp5/dt: Make use of chipset devicetree
......................................................................

mb/system76/oryp5/dt: Make use of chipset devicetree

Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.

Change-Id: I4769f255ce5652a9969ad6535c997ec1ad0be8d2
Signed-off-by: Felix Singer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78839
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Crawford 
---
M src/mainboard/system76/oryp5/devicetree.cb
1 file changed, 19 insertions(+), 63 deletions(-)

Approvals:
  Tim Crawford: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb
index ae52165..13da8f1 100644
--- a/src/mainboard/system76/oryp5/devicetree.cb
+++ b/src/mainboard/system76/oryp5/devicetree.cb
@@ -60,23 +60,19 @@

device domain 0 on
    	subsystemid 0x1558 0x95e6 inherit
-		device pci 00.0 on  end # Host Bridge
-		device pci 01.0 on      # GPU Port
+		device ref peg0		on
    		# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
    		register "PcieClkSrcUsage[8]" = "0x40"
    		register "PcieClkSrcClkReq[8]" = "8"
    	end
-		device pci 02.0 on      # Integrated Graphics Device
+		device ref igpu		on
    		register "gfx" = "GMA_DEFAULT_PANEL(0)"
    	end
-		device pci 04.0 on      # SA Thermal device
+		device ref dptf		on
    		register "Device4Enable" = "1"
    	end
-		device pci 12.0 on  end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 13.0 off end # Integrated Sensor Hub
-		device pci 14.0 on      # USB xHCI
+		device ref thermal	on	end
+		device ref xhci		on
    		register "usb2_ports" = "{
    			[0] = USB2_PORT_TYPE_C(OC_SKIP),	/* Type-C */
    			[1] = USB2_PORT_TYPE_C(OC_SKIP),	/* Type-C/DP */
@@ -96,95 +92,59 @@
    			[6] = USB3_PORT_DEFAULT(OC_SKIP),	/* 3G/LTE */
    		}"
    	end
-		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.2 on  end # Shared SRAM
-		device pci 14.3 on      # CNVi wifi
+		device ref shared_sram	on	end
+		device ref cnvi_wifi	on
    		#chip drivers/intel/wifi
    		#	register "wake" = "PME_B0_EN_BIT"
    		#end
    	end
-		device pci 14.5 off end # SDCard
-		device pci 15.0 on      # I2C #0
+		device ref i2c0		on
    		# I2C HID not supported on PNP0f13
    	end
-		device pci 15.1 on  end # I2C #1
-		device pci 15.2 off end # I2C #2
-		device pci 15.3 off end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 on      # SATA
+		device ref i2c1		on	end
+		device ref sata		on
    		register "SataPortsEnable" = "{
    			[1] = 1, /* SSD (SATA1A) */
    			[4] = 1, /* HDD (SATA4) */
    		}"
    	end
-		device pci 19.0 off end # I2C #4
-		device pci 19.1 off end # I2C #5
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 off end # eMMC
-		device pci 1b.0 off end # PCI Express Port 17
-		device pci 1b.1 off end # PCI Express Port 18
-		device pci 1b.2 off end # PCI Express Port 19
-		device pci 1b.3 off end # PCI Express Port 20
-		device pci 1b.4 on      # PCI Express Port 21
+		device ref uart2	on	end
+		device ref pcie_rp21	on
    		# PCI Express root port #21 x4, Clock 11 (SSD2)
    		register "PcieRpEnable[20]" = "1"
    		register "PcieRpLtrEnable[20]" = "1"
    		register "PcieClkSrcUsage[11]" = "20"
    		register "PcieClkSrcClkReq[11]" = "11"
    	end
-		device pci 1b.5 off end # PCI Express Port 22
-		device pci 1b.6 off end # PCI Express Port 23
-		device pci 1b.7 off end # PCI Express Port 24
-		device pci 1c.0 off end # PCI Express Port 1
-		device pci 1c.1 off end # PCI Express Port 2
-		device pci 1c.2 off end # PCI Express Port 3
-		device pci 1c.3 off end # PCI Express Port 4
-		device pci 1c.4 off end # PCI Express Port 5
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on      # PCI Express Port 9
+		device ref pcie_rp9	on
    		# PCI Express root port #9 x4, Clock 12 (SSD)
    		register "PcieRpEnable[8]" = "1"
    		register "PcieRpLtrEnable[8]" = "1"
    		register "PcieClkSrcUsage[12]" = "8"
    		register "PcieClkSrcClkReq[12]" = "12"
    	end
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 on      # PCI Express Port 14
+		device ref pcie_rp14	on
    		# PCI Express root port #14 x1, Clock 13 (WLAN)
    		register "PcieRpEnable[13]" = "1"
    		register "PcieRpLtrEnable[13]" = "1"
    		register "PcieClkSrcUsage[13]" = "13"
    		register "PcieClkSrcClkReq[13]" = "13"
    	end
-		device pci 1d.6 on      # PCI Express Port 15
+		device ref pcie_rp15	on
    		# PCI Express root port #15 x1, Clock 14 (GLAN)
    		register "PcieRpEnable[14]" = "1"
    		register "PcieRpLtrEnable[14]" = "1"
    		register "PcieClkSrcUsage[14]" = "14"
    		register "PcieClkSrcClkReq[14]" = "14"
    	end
-		device pci 1d.7 on      # PCI Express Port 16
+		device ref pcie_rp16	on
    		# PCI Express root port #16 x1, Clock 15 (Card Reader)
    		register "PcieRpEnable[15]" = "1"
    		register "PcieRpLtrEnable[15]" = "1"
    		register "PcieClkSrcUsage[15]" = "15"
    		register "PcieClkSrcClkReq[15]" = "15"
    	end
-		device pci 1e.0 off end # UART #0
-		device pci 1e.1 off end # UART #1
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 off end # GSPI #1
-		device pci 1f.0 on # LPC Interface
+		device ref lpc_espi	on
    		register "gen1_dec" = "0x00040069"
    		register "gen2_dec" = "0x00fc0e01"
    		register "gen3_dec" = "0x00fc0f01"
@@ -192,19 +152,15 @@
    			device pnp 0c31.0 on end
    		end
    	end
-		device pci 1f.1 off end # P2SB
-		device pci 1f.2 hidden end # Power Management Controller
-		device pci 1f.3 on      # Intel HDA
+		device ref hda		on
    		subsystemid 0x1558 0x96e1
    		register "PchHdaAudioLinkHda" = "1"
    	end
-		device pci 1f.4 on      # SMBus
+		device ref smbus	on
    		chip drivers/i2c/tas5825m
    			register "id" = "0"
    			device i2c 4e on end # (8bit address: 0x9c)
    		end # tas5825m
    	end
-		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 off end # GbE
    end
 end