Altamshali Hirani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62910 )
Change subject: Update Coreboot.org PSP Firmware Integration Guide Documentation ......................................................................
Update Coreboot.org PSP Firmware Integration Guide Documentation
Update Coreboot.org PSP Firmware Documentation with current internal PSP documentation
Signed-off-by: Altamshali Hirani al.hirani@amd.corp-partner.google.com Change-Id: I677f86614b0fdc6377fb2e27932ed3a8ded27102 --- M Documentation/soc/amd/psp_integration.md 1 file changed, 16 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/62910/1
diff --git a/Documentation/soc/amd/psp_integration.md b/Documentation/soc/amd/psp_integration.md index 9c7b1be..3e9dd07 100755 --- a/Documentation/soc/amd/psp_integration.md +++ b/Documentation/soc/amd/psp_integration.md @@ -172,6 +172,10 @@ * Intermediate Key Encryption Key, used to decrypt encrypted firmware images. This is mandatory in order to support encrypted firmware.
+**0x22**: PSP Token Unlock data +* Used to support time-bound Secure Debug unlock during boot. This entry may + be omitted if the Token Unlock debug feature is not required. + **0x24**: Security policy binary * A security policy is applied to restrict the untrusted access to security sensitive regions. @@ -200,10 +204,6 @@ **0x52**: PSP boot loader usermode OEM application * Supported only in certain SKUs.
-**0x22**: PSP Token Unlock data -* Used to support time-bound Secure Debug unlock during boot. This entry may - be omitted if the Token Unlock debug feature is not required. - ### Firmware Version of Binaries
Every firmware binary contains 256 bytes of a PSP Header, which includes @@ -302,15 +302,25 @@ +--------------+---------------+------------------+----------------------------+ | SubProgram | 0x03[2:0] | 3 | Specify the SubProgram | +--------------+---------------+------------------+----------------------------+ -| Reserved | 0x03[7:3] | 5 | Reserved - Set to zero | +| RomId | 0x03[4:3] | 2 | Which SPI device the | +| | | | content is placed in ++--------------+---------------+------------------+----------------------------+ +| Writeable | 0x03[5] | 1 | Region is writable or read | +| | | | only | ++--------------+---------------+------------------+----------------------------+ +| Reserved | 0x03[7:6] | 2 | Reserved - Set to zero | +--------------+---------------+------------------+----------------------------+ | Size | 0x04 | 32 | Memory Region Size | +--------------+---------------+------------------+----------------------------+ -| Source | 0x08 | 64 | Physical Address of SPIROM | +| Source | 0x08 | 62 | Physical Address of SPIROM | | Address | | | location where the data for| | | | | the corresponding entry is | | | | | located | +--------------+---------------+------------------+----------------------------+ +| Entry Address| 0x08 | 2 | Same as Entry Address Mode | +| Mode | | | in PSP directory table | +| | | | entry fields | ++--------------+---------------+------------------+----------------------------+ | Destination | 0x10 | 64 | Destination Address of | | Address | | | memory location where the | | | | | data for the corresponding |