Change in coreboot[master]: Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com> C...
Julia Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 ......................................................................
Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 --- A src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/gpio.c 2 files changed, 161 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44079/1
diff --git a/src/mainboard/google/volteer/variants/lindar/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/Makefile.inc new file mode 100644 index 0000000..776c4ea --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/lindar/gpio.c b/src/mainboard/google/volteer/variants/lindar/gpio.c new file mode 100644 index 0000000..e0f93ab --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/gpio.c @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A22 : DDPC_CTRLDATA ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> NOT USED */ + PAD_NC(GPP_B2, NONE), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> NOT USED */ + PAD_NC(GPP_B22, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_CVF_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> SPKR_INT_R */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L_CAP_SITE */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +}
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44079
to look at the new patch set (#2).
Change subject: mb/google/volteer/variant/lindar: Update gpio settings ......................................................................
mb/google/volteer/variant/lindar: Update gpio settings
Based on schematic and gpio table of lindar, generate gpio settings for lindar.
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 --- A src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/gpio.c 2 files changed, 161 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44079/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio settings ......................................................................
Patch Set 2:
I'd prefer if this could be squashed into the parent
Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio settings ......................................................................
Patch Set 2: Code-Review+1
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44079
to look at the new patch set (#3).
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
mb/google/volteer/variant/lindar: Update gpio and devicetree settings
Based on schematic and gpio table of lindar, generate gpio and overridetree.cb settings for lindar.
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 --- A src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/gpio.c M src/mainboard/google/volteer/variants/lindar/overridetree.cb 3 files changed, 274 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44079/3
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44079
to look at the new patch set (#4).
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
mb/google/volteer/variant/lindar: Update gpio and devicetree settings
Based on schematic and gpio table of lindar, generate gpio and overridetree.cb settings for lindar.
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 --- A src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/gpio.c M src/mainboard/google/volteer/variants/lindar/overridetree.cb 3 files changed, 273 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44079/4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 4: Code-Review+1
This should be rebased. There's a button in Gerrit around the top right quadrant, under the search bar, that says `Rebase`. Choose `Rebase on parent change`.
Rasheed Hsueh has uploaded a new patch set (#6) to the change originally created by Julia Tsai. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
mb/google/volteer/variant/lindar: Update gpio and devicetree settings
Based on schematic and gpio table of lindar, generate gpio and overridetree.cb settings for lindar.
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 --- A src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/gpio.c M src/mainboard/google/volteer/variants/lindar/overridetree.cb 3 files changed, 273 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44079/6
Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 6:
Please fix the error:
src/mainboard/google/volteer/variants/lindar/overridetree.cb has no final newline.
Rasheed Hsueh has uploaded a new patch set (#7) to the change originally created by Julia Tsai. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
mb/google/volteer/variant/lindar: Update gpio and devicetree settings
Based on schematic and gpio table of lindar, generate gpio and overridetree.cb settings for lindar.
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 --- A src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/gpio.c M src/mainboard/google/volteer/variants/lindar/overridetree.cb 3 files changed, 272 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44079/7
Rasheed Hsueh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 7:
Patch Set 6:
Please fix the error:
src/mainboard/google/volteer/variants/lindar/overridetree.cb has no final newline.
done
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 7: Code-Review+1
Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 7:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lindar/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... PS7, Line 13: register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 Please add a newline to seperate usb2 and usb3 setting.
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... PS7, Line 17: register "SaGv" = "SaGv_Disabled" Please add a newline to seperate the different setting.
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... PS7, Line 64: device pci 15.2 on : chip drivers/i2c/sx9310 : register "desc" = ""SAR0 Proximity Sensor"" : register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" : register "speed" = "I2C_SPEED_FAST" : register "uid" = "0" : register "reg_prox_ctrl0" = "0x10" : register "reg_prox_ctrl1" = "0x00" : register "reg_prox_ctrl2" = "0x84" : register "reg_prox_ctrl3" = "0x0e" : register "reg_prox_ctrl4" = "0x07" : register "reg_prox_ctrl5" = "0xc6" : register "reg_prox_ctrl6" = "0x20" : register "reg_prox_ctrl7" = "0x0d" : register "reg_prox_ctrl8" = "0x8d" : register "reg_prox_ctrl9" = "0x43" : register "reg_prox_ctrl10" = "0x1f" : register "reg_prox_ctrl11" = "0x00" : register "reg_prox_ctrl12" = "0x00" : register "reg_prox_ctrl13" = "0x00" : register "reg_prox_ctrl14" = "0x00" : register "reg_prox_ctrl15" = "0x00" : register "reg_prox_ctrl16" = "0x00" : register "reg_prox_ctrl17" = "0x00" : register "reg_prox_ctrl18" = "0x00" : register "reg_prox_ctrl19" = "0x00" : register "reg_sar_ctrl0" = "0x50" : register "reg_sar_ctrl1" = "0x8a" : register "reg_sar_ctrl2" = "0x3c" : device i2c 28 on end : end : end # I2C2 0xA0EA I don't think you have the proximity sensor, could you please double check this?
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... PS7, Line 106: device pci 1f.3 on : chip drivers/generic/max98357a : register "hid" = ""MX98357A"" : register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" : register "sdmode_delay" = "5" : device generic 0 on end : end : end # Intel HD audio Are you using max98357a?
Rasheed Hsueh has uploaded a new patch set (#8) to the change originally created by Julia Tsai. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
mb/google/volteer/variant/lindar: Update gpio and devicetree settings
Based on schematic and gpio table of lindar, generate gpio and overridetree.cb settings for lindar.
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 Signed-off-by: rasheed.hsueh rasheed.hsueh@lcfc.corp-partner.google.com --- A src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/gpio.c M src/mainboard/google/volteer/variants/lindar/overridetree.cb 3 files changed, 233 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44079/8
Rasheed Hsueh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 8:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lindar/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... PS7, Line 13: register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0
Please add a newline to seperate usb2 and usb3 setting.
Done
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... PS7, Line 17: register "SaGv" = "SaGv_Disabled"
Please add a newline to seperate the different setting.
Done
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... PS7, Line 64: device pci 15.2 on : chip drivers/i2c/sx9310 : register "desc" = ""SAR0 Proximity Sensor"" : register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" : register "speed" = "I2C_SPEED_FAST" : register "uid" = "0" : register "reg_prox_ctrl0" = "0x10" : register "reg_prox_ctrl1" = "0x00" : register "reg_prox_ctrl2" = "0x84" : register "reg_prox_ctrl3" = "0x0e" : register "reg_prox_ctrl4" = "0x07" : register "reg_prox_ctrl5" = "0xc6" : register "reg_prox_ctrl6" = "0x20" : register "reg_prox_ctrl7" = "0x0d" : register "reg_prox_ctrl8" = "0x8d" : register "reg_prox_ctrl9" = "0x43" : register "reg_prox_ctrl10" = "0x1f" : register "reg_prox_ctrl11" = "0x00" : register "reg_prox_ctrl12" = "0x00" : register "reg_prox_ctrl13" = "0x00" : register "reg_prox_ctrl14" = "0x00" : register "reg_prox_ctrl15" = "0x00" : register "reg_prox_ctrl16" = "0x00" : register "reg_prox_ctrl17" = "0x00" : register "reg_prox_ctrl18" = "0x00" : register "reg_prox_ctrl19" = "0x00" : register "reg_sar_ctrl0" = "0x50" : register "reg_sar_ctrl1" = "0x8a" : register "reg_sar_ctrl2" = "0x3c" : device i2c 28 on end : end : end # I2C2 0xA0EA
I don't think you have the proximity sensor, could you please double check this?
remove proximity sensor
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... PS7, Line 106: device pci 1f.3 on : chip drivers/generic/max98357a : register "hid" = ""MX98357A"" : register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" : register "sdmode_delay" = "5" : device generic 0 on end : end : end # Intel HD audio
Are you using max98357a?
Thanks for reminding us, we exchange to use the Realtek ALC 1011 for the future. Remove this block of the max98357a. Waiting for a new schematic with ALC 1011, I will create a new issue/CL to update the device tree files.
Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lindar/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... PS7, Line 22: PchSerialIoPci Since you are not using the proximity sensor, i think you can disable this.
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... PS7, Line 64: device pci 15.2 on : chip drivers/i2c/sx9310 : register "desc" = ""SAR0 Proximity Sensor"" : register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" : register "speed" = "I2C_SPEED_FAST" : register "uid" = "0" : register "reg_prox_ctrl0" = "0x10" : register "reg_prox_ctrl1" = "0x00" : register "reg_prox_ctrl2" = "0x84" : register "reg_prox_ctrl3" = "0x0e" : register "reg_prox_ctrl4" = "0x07" : register "reg_prox_ctrl5" = "0xc6" : register "reg_prox_ctrl6" = "0x20" : register "reg_prox_ctrl7" = "0x0d" : register "reg_prox_ctrl8" = "0x8d" : register "reg_prox_ctrl9" = "0x43" : register "reg_prox_ctrl10" = "0x1f" : register "reg_prox_ctrl11" = "0x00" : register "reg_prox_ctrl12" = "0x00" : register "reg_prox_ctrl13" = "0x00" : register "reg_prox_ctrl14" = "0x00" : register "reg_prox_ctrl15" = "0x00" : register "reg_prox_ctrl16" = "0x00" : register "reg_prox_ctrl17" = "0x00" : register "reg_prox_ctrl18" = "0x00" : register "reg_prox_ctrl19" = "0x00" : register "reg_sar_ctrl0" = "0x50" : register "reg_sar_ctrl1" = "0x8a" : register "reg_sar_ctrl2" = "0x3c" : device i2c 28 on end : end : end # I2C2 0xA0EA
remove proximity sensor
I think you can set it to off.
rasheed.hsueh has uploaded a new patch set (#9) to the change originally created by Julia Tsai. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
mb/google/volteer/variant/lindar: Update gpio and devicetree settings
Based on schematic and gpio table of lindar, generate gpio and overridetree.cb settings for lindar.
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 Signed-off-by: rasheed.hsueh rasheed.hsueh@lcfc.corp-partner.google.com --- A src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/gpio.c M src/mainboard/google/volteer/variants/lindar/overridetree.cb 3 files changed, 234 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44079/9
Rasheed Hsueh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lindar/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... PS7, Line 22: PchSerialIoPci
Since you are not using the proximity sensor, i think you can disable this.
Done
https://review.coreboot.org/c/coreboot/+/44079/7/src/mainboard/google/voltee... PS7, Line 64: device pci 15.2 on : chip drivers/i2c/sx9310 : register "desc" = ""SAR0 Proximity Sensor"" : register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" : register "speed" = "I2C_SPEED_FAST" : register "uid" = "0" : register "reg_prox_ctrl0" = "0x10" : register "reg_prox_ctrl1" = "0x00" : register "reg_prox_ctrl2" = "0x84" : register "reg_prox_ctrl3" = "0x0e" : register "reg_prox_ctrl4" = "0x07" : register "reg_prox_ctrl5" = "0xc6" : register "reg_prox_ctrl6" = "0x20" : register "reg_prox_ctrl7" = "0x0d" : register "reg_prox_ctrl8" = "0x8d" : register "reg_prox_ctrl9" = "0x43" : register "reg_prox_ctrl10" = "0x1f" : register "reg_prox_ctrl11" = "0x00" : register "reg_prox_ctrl12" = "0x00" : register "reg_prox_ctrl13" = "0x00" : register "reg_prox_ctrl14" = "0x00" : register "reg_prox_ctrl15" = "0x00" : register "reg_prox_ctrl16" = "0x00" : register "reg_prox_ctrl17" = "0x00" : register "reg_prox_ctrl18" = "0x00" : register "reg_prox_ctrl19" = "0x00" : register "reg_sar_ctrl0" = "0x50" : register "reg_sar_ctrl1" = "0x8a" : register "reg_sar_ctrl2" = "0x3c" : device i2c 28 on end : end : end # I2C2 0xA0EA
I think you can set it to off.
Done
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44079/9/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lindar/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44079/9/src/mainboard/google/voltee... PS9, Line 49: chip drivers/i2c/hid please update goodix settings from volteer.
Rasheed Hsueh has uploaded a new patch set (#10) to the change originally created by Julia Tsai. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
mb/google/volteer/variant/lindar: Update gpio and devicetree settings
Based on schematic and gpio table of lindar, generate gpio and overridetree.cb settings for lindar.
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 Signed-off-by: rasheed.hsueh rasheed.hsueh@lcfc.corp-partner.google.com --- A src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/gpio.c M src/mainboard/google/volteer/variants/lindar/overridetree.cb 3 files changed, 233 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44079/10
Rasheed Hsueh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44079/9/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lindar/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44079/9/src/mainboard/google/voltee... PS9, Line 49: chip drivers/i2c/hid
please update goodix settings from volteer.
Done
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44079/10/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/lindar/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44079/10/src/mainboard/google/volte... PS10, Line 60: register "generic.has_power_resource" = "1" i think you still need to copy over the stop_gpio related config. looks like it's the same GPP_E3 for lindar.
Rasheed Hsueh has uploaded a new patch set (#11) to the change originally created by Julia Tsai. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
mb/google/volteer/variant/lindar: Update gpio and devicetree settings
Based on schematic and gpio table of lindar, generate gpio and overridetree.cb settings for lindar.
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 Signed-off-by: rasheed.hsueh rasheed.hsueh@lcfc.corp-partner.google.com --- A src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/gpio.c M src/mainboard/google/volteer/variants/lindar/overridetree.cb 3 files changed, 239 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44079/11
Rasheed Hsueh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44079/10/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/lindar/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44079/10/src/mainboard/google/volte... PS10, Line 60: register "generic.has_power_resource" = "1"
i think you still need to copy over the stop_gpio related config. […]
Done
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 11: Code-Review+1
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44079/11/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/lindar/gpio.c:
https://review.coreboot.org/c/coreboot/+/44079/11/src/mainboard/google/volte... PS11, Line 23: /* A22 : DDPC_CTRLDATA ==> EN_PP3300_SSD */ : PAD_CFG_GPO(GPP_A22, 1, DEEP), you'll also want to set this in early_gpio, see volteer for reference.
Rasheed Hsueh has uploaded a new patch set (#12) to the change originally created by Julia Tsai. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
mb/google/volteer/variant/lindar: Update gpio and devicetree settings
Based on schematic and gpio table of lindar, generate gpio and overridetree.cb settings for lindar.
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 Signed-off-by: rasheed.hsueh rasheed.hsueh@lcfc.corp-partner.google.com --- A src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/gpio.c M src/mainboard/google/volteer/variants/lindar/overridetree.cb 3 files changed, 235 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44079/12
Rasheed Hsueh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44079/11/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/lindar/gpio.c:
https://review.coreboot.org/c/coreboot/+/44079/11/src/mainboard/google/volte... PS11, Line 23: /* A22 : DDPC_CTRLDATA ==> EN_PP3300_SSD */ : PAD_CFG_GPO(GPP_A22, 1, DEEP),
you'll also want to set this in early_gpio, see volteer for reference.
Done, add settings to early_gpio.
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 12: Code-Review+1
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 12: Code-Review+1
Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
Patch Set 12: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44079 )
Change subject: mb/google/volteer/variant/lindar: Update gpio and devicetree settings ......................................................................
mb/google/volteer/variant/lindar: Update gpio and devicetree settings
Based on schematic and gpio table of lindar, generate gpio and overridetree.cb settings for lindar.
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Julia Tsai julia.tsai@lcfc.corp-partner.google.com Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 Signed-off-by: rasheed.hsueh rasheed.hsueh@lcfc.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44079 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Reviewed-by: Zhuohao Lee zhuohao@chromium.org --- A src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/gpio.c M src/mainboard/google/volteer/variants/lindar/overridetree.cb 3 files changed, 235 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, but someone else must approve Zhuohao Lee: Looks good to me, approved Paul Fagerburg: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/lindar/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/Makefile.inc new file mode 100644 index 0000000..776c4ea --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/lindar/gpio.c b/src/mainboard/google/volteer/variants/lindar/gpio.c new file mode 100644 index 0000000..4f3d5f7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/gpio.c @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A22 : DDPC_CTRLDATA ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> NOT USED */ + PAD_NC(GPP_B2, NONE), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> NOT USED */ + PAD_NC(GPP_B22, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_CVF_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> SPKR_INT_R */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L_CAP_SITE */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 32204c5..6f14622 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -1,6 +1,83 @@ chip soc/intel/tigerlake + # USB Port Config + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + + register "SaGv" = "SaGv_Disabled" + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" device domain 0 on + device pci 07.0 off end # TBT_PCIe0 0x9A23 + device pci 07.1 off end # TBT_PCIe1 0x9A25 + device pci 07.2 off end # TBT_PCIe2 0x9A27 + device pci 07.3 off end # TBT_PCIe3 0x9A29 + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C0 + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + # Parameter T3 >= 10ms + register "generic.reset_delay_ms" = "120" + # Parameter T2 >= 1ms + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + # Parameter T1 >= 10ms + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + end # I2C1 + device pci 15.2 off end # I2C2 0xA0EA + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end # I2C5 0xA0C6 end - end
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