Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85805?usp=email )
Change subject: soc/intel/xeon_sp/skx: Enable x86_64 ......................................................................
soc/intel/xeon_sp/skx: Enable x86_64
On Xeon Skylake-SP with dual sockets the platforms make use of 46bit of the address space. Most of the PCI BARs reside in high MMIO, not reachable by x86_32 coreboot.
Add support for x86_64 coreboot and confirm that all supported boards are booting without errors. This is done by converting all occurence of VOID * to UINT32 to make sure that FSP UPDs do not change when pointers are 8byte wide.
TEST: Booted on ocp/tiogapass to Linux. No errors were observed.
Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/ocp/tiogapass/romstage.c M src/soc/intel/xeon_sp/skx/Kconfig M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h 3 files changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85805/1
diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index 283d5f1..cae6815 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -17,6 +17,9 @@
static void oem_update_iio(FSPM_UPD *mupd) { + UPD_IIO_BIFURCATION_DATA_ENTRY *entry = + (void *)(uintptr_t)mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTablePtr; + /* Read GPIO to decide IIO bifurcation at run-time. */ int slot_config0 = gpio_get(GPP_C15); int slot_config1 = gpio_get(GPP_C16); @@ -25,25 +28,24 @@ reading the GPIO expander PCA9555 via SMBUS, and then configure the bifurcation accordingly is left for future work. */ if (!slot_config0 && slot_config1) - mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable[Skt0_Iou0].Bifurcation - = IIO_BIFURCATE_xxx8xxx8; + entry[Skt0_Iou0].Bifurcation = IIO_BIFURCATE_xxx8xxx8; }
static void mainboard_config_iio(FSPM_UPD *mupd) { memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table)); - mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable = - (UPD_IIO_BIFURCATION_DATA_ENTRY *)iio_table_buf; + mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTablePtr = + (uintptr_t)(UPD_IIO_BIFURCATION_DATA_ENTRY *)iio_table_buf; mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries = ARRAY_SIZE(tp_iio_bifur_table);
- mupd->FspmConfig.IioPciConfig.ConfigurationTable = - (UPD_PCI_PORT_CONFIG *)tp_iio_pci_port_skt0; + mupd->FspmConfig.IioPciConfig.ConfigurationTablePtr = + (uintptr_t)(UPD_PCI_PORT_CONFIG *)tp_iio_pci_port_skt0; mupd->FspmConfig.IioPciConfig.NumberOfEntries = ARRAY_SIZE(tp_iio_pci_port_skt0);
- mupd->FspmConfig.PchPciConfig.PciPortConfig = - (UPD_PCH_PCIE_PORT *)tp_pch_pci_port_skt0; + mupd->FspmConfig.PchPciConfig.PciPortConfigPtr = + (uintptr_t)(UPD_PCH_PCIE_PORT *)tp_pch_pci_port_skt0; mupd->FspmConfig.PchPciConfig.NumberOfEntries = ARRAY_SIZE(tp_pch_pci_port_skt0);
@@ -62,7 +64,7 @@ mainboard_config_iio(mupd);
/* do not configure GPIO controller inside FSP-M */ - mupd->FspmConfig.GpioConfig.GpioTable = NULL; + mupd->FspmConfig.GpioConfig.GpioTablePtr = 0; mupd->FspmConfig.GpioConfig.NumberOfEntries = 0; }
diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 970dba3..acbc31f 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -6,6 +6,8 @@ select PLATFORM_USES_FSP2_0 select NO_FSP_TEMP_RAM_EXIT select UDK_202005_BINDING + select HAVE_X86_64_SUPPORT + select USE_X86_64_SUPPORT help Intel Skylake-SP support
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h index f81e218..8306106 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h @@ -261,7 +261,7 @@ /** GPIOTABLE_CONFIG: GpioTable - Base Address of the Gpio Table declared by the - bootloader. + bootloader. Pointer to UPD_GPIO_INIT_CONFIG. Default: NULL NumberofEntries - Number of Entries in the GPIO Table provided Default: 0 @@ -269,7 +269,7 @@ configuration using default GPIO_INIT_CONFIG tables **/ typedef struct { - UPD_GPIO_INIT_CONFIG *GpioTable; + UINT32 GpioTablePtr; UINT32 NumberOfEntries; } GPIOTABLE_CONFIG;
@@ -293,7 +293,7 @@ /** IIOBIFURCATION_CONFIG: IIoBifurcationTable - Base Address of the IIO Bifurcation table - declared by the bootloader + declared by the bootloader. Pointer to UPD_IIO_BIFURCATION_DATA_ENTRY. Default: NULL NumberofEntries - Number of Entries in the IIO Bifurcation Table Default: 0 @@ -301,7 +301,7 @@ bifurcation using default IIO_BIFURCATION_DATA_ENTRY tables **/ typedef struct { - UPD_IIO_BIFURCATION_DATA_ENTRY *IIoBifurcationTable; + UINT32 IIoBifurcationTablePtr; UINT32 NumberOfEntries; } IIOBIFURCATION_CONFIG;
@@ -381,12 +381,11 @@ /** PCIEPORT_CONFIG: PciePortConfiguration - Pointer to an array of PCIe port configuration structures - as declared above + as declared above. Pointer to UPD_PCI_PORT_CONFIG. NumberOfEntries - Number of elements in the PciePortConfiguration Array **/ typedef struct { - UPD_PCI_PORT_CONFIG *ConfigurationTable; - + UINT32 ConfigurationTablePtr; UINT16 NumberOfEntries; } IIOPCIPORT_CONFIG;
@@ -412,11 +411,12 @@
/** IIORESOURCE_CONFIG: - ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array + ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array. + Pointer to UPD_IIO_STACK_RESOURCE_CONFIG. NumberOfEntries - Number of Entries in the Iio Stack Resource Configuration Array **/ typedef struct { - UPD_IIO_STACK_RESOURCE_CONFIG *ResourceTable; + UINT32 ResourceTablePtr; UINT16 NumberOfEntries; } IIORESOURCE_CONFIG;
@@ -436,6 +436,7 @@ /** PCHPCIPORT_CONFIG: PciPortConfig - Pointer to an array of PCH PCI Ports to be configured + Pointer to UPD_PCH_PCIE_PORT. RootPortFunctionSwapping - Disable root port swapping based on device connection status PciePllSsc - Specifies the Pcie Pll Spread Spectrum Percentage @@ -446,7 +447,7 @@ NumberOfEntries - Number of entries in the PCH PCI Port configuration **/ typedef struct { - UPD_PCH_PCIE_PORT *PciPortConfig; + UINT32 PciPortConfigPtr; UINT8 RootPortFunctionSwapping; UINT8 PciePllSsc; UINT16 NumberOfEntries; @@ -507,12 +508,7 @@ **/ UINT8 BoardId;
- UINT8 reserved2[24]; - -/** Offset 0x00C2 **/ - VOID *SetupStructPtr; - - UINT8 reserved3[20]; + UINT8 reserved2[48];
/** Offset 0x00DA - IioPciConfig IIO Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero. @@ -529,7 +525,7 @@ **/ IIORESOURCE_CONFIG IioResourceConfig;
- UINT8 reserved4[3]; + UINT8 reserved3[3];
/** Offset 0x00F1 - DCI Enable Enable / Disable DCI
-
Patrick Rudolph (Code Review)